6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-16 14:31:59 +00:00
Code Issues Projects Releases Wiki Activity

Add extra SEXT pattern.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77920 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne 2009-08-02 22:45:24 +00:00
parent 3bb9b9a1ab
commit d558ea5e0a
2 changed files with 48 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
lib/Target/XCore/XCoreInstrInfo.td
View File

@ -95,6 +95,12 @@ def neg_xform : SDNodeXForm<imm, [{
return getI32Imm(-value);
}]>;
def bpwsub_xform : SDNodeXForm<imm, [{
// Transformation function: 32-imm
uint32_t value = N->getZExtValue();
return getI32Imm(32-value);
}]>;
def div4neg_xform : SDNodeXForm<imm, [{
// Transformation function: -imm/4
uint32_t value = N->getZExtValue();
@ -162,6 +168,14 @@ def immBitp : PatLeaf<(imm), [{
|| value == 32;
}]>;
def immBpwSubBitp : PatLeaf<(imm), [{
uint32_t value = (uint32_t)N->getZExtValue();
return (value >= 24 && value <= 31)
|| value == 16
|| value == 8
|| value == 0;
}]>;
def lda16f : PatFrag<(ops node:$addr, node:$offset),
(add node:$addr, (shl node:$offset, 1))>;
def lda16b : PatFrag<(ops node:$addr, node:$offset),
@ -989,3 +1003,5 @@ def : Pat<(mul GRRegs:$src, -3),
def : Pat<(sra GRRegs:$src, 31),
(ASHR_l2rus GRRegs:$src, 32)>;
def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm),
(SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>;

32
test/CodeGen/XCore/sext.ll Normal file
View File

@ -0,0 +1,32 @@
; RUN: llvm-as < %s | llc -march=xcore | FileCheck %s
define i32 @sext1(i32 %a) {
%1 = trunc i32 %a to i1
%2 = sext i1 %1 to i32
ret i32 %2
}
; CHECK: sext1:
; CHECK: sext r0, 1
define i32 @sext2(i32 %a) {
%1 = trunc i32 %a to i2
%2 = sext i2 %1 to i32
ret i32 %2
}
; CHECK: sext2:
; CHECK: sext r0, 2
define i32 @sext8(i32 %a) {
%1 = trunc i32 %a to i8
%2 = sext i8 %1 to i32
ret i32 %2
}
; CHECK: sext8:
; CHECK: sext r0, 8
define i32 @sext16(i32 %a) {
%1 = trunc i32 %a to i16
%2 = sext i16 %1 to i32
ret i32 %2
}
; CHECK: sext16:
; CHECK: sext r0, 16