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Fix ARM disassembly for PLD/PLDW/PLI which suffers from code rot and add some test cases.

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Add comments to ThumbDisassemblerCore.h for recent change made for t2PLD disassembly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128417 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen
2011-03-28 18:41:58 +00:00
parent 93f7936435
commit d560a80925
3 changed files with 27 additions and 5 deletions
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17
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
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@ -2893,8 +2893,8 @@ static bool DisassemblePreLoadFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
unsigned short NumOps, unsigned &NumOpsAdded, BO B) { unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
// Preload Data/Instruction requires either 2 or 3 operands. // Preload Data/Instruction requires either 2 or 3 operands.
// PLDi, PLDWi, PLIi: addrmode_imm12 // PLDi12, PLDWi12, PLIi12: addrmode_imm12
// PLDr[a|m], PLDWr[a|m], PLIr[a|m]: ldst_so_reg // PLDrs, PLDWrs, PLIrs: ldst_so_reg
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
decodeRn(insn)))); decodeRn(insn))));
@ -2903,10 +2903,19 @@ static bool DisassemblePreLoadFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
|| Opcode == ARM::PLIi12) { || Opcode == ARM::PLIi12) {
unsigned Imm12 = slice(insn, 11, 0); unsigned Imm12 = slice(insn, 11, 0);
bool Negative = getUBit(insn) == 0; bool Negative = getUBit(insn) == 0;
// A8.6.118 PLD (literal) PLDWi12 with Rn=PC is transformed to PLDi12.
if (Opcode == ARM::PLDWi12 && slice(insn, 19, 16) == 0xF) {
DEBUG(errs() << "Rn == '1111': PLDWi12 morphed to PLDi12\n");
MI.setOpcode(ARM::PLDi12);
}
// -0 is represented specially. All other values are as normal. // -0 is represented specially. All other values are as normal.
int Offset = Negative ? -1 * Imm12 : Imm12;
if (Imm12 == 0 && Negative) if (Imm12 == 0 && Negative)
Imm12 = INT32_MIN; Offset = INT32_MIN;
MI.addOperand(MCOperand::CreateImm(Imm12));
MI.addOperand(MCOperand::CreateImm(Offset));
NumOpsAdded = 2; NumOpsAdded = 2;
} else { } else {
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID, MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,

6
lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
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@ -1799,8 +1799,12 @@ static bool DisassembleThumb2PreLoad(MCInst &MI, unsigned Opcode, uint32_t insn,
// A8.6.117 Encoding T2: add = FALSE // A8.6.117 Encoding T2: add = FALSE
unsigned Imm8 = getImm8(insn); unsigned Imm8 = getImm8(insn);
Offset = -1 * Imm8; Offset = -1 * Imm8;
} else // The i12 forms. See, for example, A8.6.117 Encoding T1. } else {
// The i12 forms. See, for example, A8.6.117 Encoding T1.
// Note that currently t2PLDi12 also handles the previously named t2PLDpci
// opcode, that's why we use decodeImm12(insn) which returns +/- imm12.
Offset = decodeImm12(insn); Offset = decodeImm12(insn);
}
MI.addOperand(MCOperand::CreateImm(Offset)); MI.addOperand(MCOperand::CreateImm(Offset));
} }
++OpIdx; ++OpIdx;

9
test/MC/Disassembler/ARM/arm-tests.txt
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@ -190,3 +190,12 @@
# CHECK: umull r1, r2, r3, r4 # CHECK: umull r1, r2, r3, r4
0x93 0x14 0x82 0xe0 0x93 0x14 0x82 0xe0
# CHECK: pld [pc, #-0]
0x00 0xf0 0x1f 0xf5
# CHECK: pli [pc, #-0]
0x00 0xf0 0x5f 0xf4
# CHECK: pli [r3, r1, lsl #2]
0x01 0xf1 0xd3 0xf6