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- Change TargetInstrInfo::reMaterialize to pass in TargetRegisterInfo.

Browse Source 
- If destination is a physical register and it has a subreg index, use the
  sub-register instead.
This fixes PR5423.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88745 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-11-14 02:55:43 +00:00
parent 4ec01b268e
commit d57cdd5683
13 changed files with 40 additions and 20 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
include/llvm/Target/TargetInstrInfo.h
View File

@ -21,6 +21,7 @@ namespace llvm {
class MCAsmInfo;
class TargetRegisterClass;
class TargetRegisterInfo;
class LiveVariables;
class CalleeSavedInfo;
class SDNode;
@ -224,7 +225,8 @@ public:
virtual void reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SubIdx,
const MachineInstr *Orig) const = 0;
const MachineInstr *Orig,
const TargetRegisterInfo *TRI) const = 0;
/// convertToThreeAddress - This method must be implemented by targets that
/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
@ -554,7 +556,8 @@ public:
virtual void reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SubReg,
const MachineInstr *Orig) const;
const MachineInstr *Orig,
const TargetRegisterInfo *TRI) const;
virtual bool isIdentical(const MachineInstr *MI,
const MachineInstr *Other,
const MachineRegisterInfo *MRI) const;

2
lib/CodeGen/PreAllocSplitting.cpp
View File

@ -881,7 +881,7 @@ bool PreAllocSplitting::Rematerialize(unsigned VReg, VNInfo* ValNo,
if (KillPt == DefMI->getParent()->end())
return false;
TII->reMaterialize(MBB, RestorePt, VReg, 0, DefMI);
TII->reMaterialize(MBB, RestorePt, VReg, 0, DefMI, TRI);
SlotIndex RematIdx = LIs->InsertMachineInstrInMaps(prior(RestorePt));
ReconstructLiveInterval(CurrLI);

2
lib/CodeGen/SimpleRegisterCoalescing.cpp
View File

@ -709,7 +709,7 @@ bool SimpleRegisterCoalescing::ReMaterializeTrivialDef(LiveInterval &SrcInt,
}
MachineBasicBlock::iterator MII = next(MachineBasicBlock::iterator(CopyMI));
tii_->reMaterialize(*MBB, MII, DstReg, DstSubIdx, DefMI);
tii_->reMaterialize(*MBB, MII, DstReg, DstSubIdx, DefMI, tri_);
MachineInstr *NewMI = prior(MII);
if (checkForDeadDef) {

11
lib/CodeGen/TargetInstrInfoImpl.cpp
View File

@ -135,11 +135,16 @@ void TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg,
unsigned SubIdx,
const MachineInstr *Orig) const {
const MachineInstr *Orig,
const TargetRegisterInfo *TRI) const {
MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
MachineOperand &MO = MI->getOperand(0);
MO.setReg(DestReg);
MO.setSubReg(SubIdx);
if (TargetRegisterInfo::isVirtualRegister(DestReg)) {
MO.setReg(DestReg);
MO.setSubReg(SubIdx);
} else {
MO.setReg(TRI->getSubReg(DestReg, SubIdx));
}
MBB.insert(I, MI);
}

2
lib/CodeGen/TwoAddressInstructionPass.cpp
View File

@ -1033,7 +1033,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist)){
DEBUG(errs() << "2addr: REMATTING : " << *DefMI << "\n");
unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg();
TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI);
TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI, TRI);
ReMatRegs.set(regB);
++NumReMats;
} else {

4
lib/CodeGen/VirtRegRewriter.cpp
View File

@ -594,7 +594,7 @@ static void UpdateKills(MachineInstr &MI, const TargetRegisterInfo* TRI,
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI.getOperand(i);
if (!MO.isReg() || !MO.isDef())
if (!MO.isReg() || !MO.getReg() || !MO.isDef())
continue;
unsigned Reg = MO.getReg();
RegKills.reset(Reg);
@ -626,7 +626,7 @@ static void ReMaterialize(MachineBasicBlock &MBB,
"Don't know how to remat instructions that define > 1 values!");
#endif
TII->reMaterialize(MBB, MII, DestReg,
ReMatDefMI->getOperand(0).getSubReg(), ReMatDefMI);
ReMatDefMI->getOperand(0).getSubReg(), ReMatDefMI, TRI);
MachineInstr *NewMI = prior(MII);
for (unsigned i = 0, e = NewMI->getNumOperands(); i != e; ++i) {
MachineOperand &MO = NewMI->getOperand(i);

9
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -921,8 +921,15 @@ void ARMBaseInstrInfo::
reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SubIdx,
const MachineInstr *Orig) const {
const MachineInstr *Orig,
const TargetRegisterInfo *TRI) const {
DebugLoc dl = Orig->getDebugLoc();
if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
DestReg = TRI->getSubReg(DestReg, SubIdx);
SubIdx = 0;
}
unsigned Opcode = Orig->getOpcode();
switch (Opcode) {
default: {

3
lib/Target/ARM/ARMBaseInstrInfo.h
View File

@ -267,7 +267,8 @@ public:
virtual void reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SubIdx,
const MachineInstr *Orig) const;
const MachineInstr *Orig,
const TargetRegisterInfo *TRI) const;
virtual bool isIdentical(const MachineInstr *MI, const MachineInstr *Other,
const MachineRegisterInfo *MRI) const;

6
lib/Target/ARM/ARMInstrInfo.cpp
View File

@ -81,8 +81,8 @@ bool ARMInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
void ARMInstrInfo::
reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SubIdx,
const MachineInstr *Orig) const {
unsigned DestReg, unsigned SubIdx, const MachineInstr *Orig,
const TargetRegisterInfo *TRI) const {
DebugLoc dl = Orig->getDebugLoc();
unsigned Opcode = Orig->getOpcode();
switch (Opcode) {
@ -100,6 +100,6 @@ reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
}
}
return ARMBaseInstrInfo::reMaterialize(MBB, I, DestReg, SubIdx, Orig);
return ARMBaseInstrInfo::reMaterialize(MBB, I, DestReg, SubIdx, Orig, TRI);
}

3
lib/Target/ARM/ARMInstrInfo.h
View File

@ -37,7 +37,8 @@ public:
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SubIdx,
const MachineInstr *Orig) const;
const MachineInstr *Orig,
const TargetRegisterInfo *TRI) const;
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
/// such, whenever a client has an instance of instruction info, it should

5
lib/Target/X86/X86InstrInfo.cpp
View File

@ -991,12 +991,13 @@ static bool isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SubIdx,
const MachineInstr *Orig) const {
const MachineInstr *Orig,
const TargetRegisterInfo *TRI) const {
DebugLoc DL = DebugLoc::getUnknownLoc();
if (I != MBB.end()) DL = I->getDebugLoc();
if (SubIdx && TargetRegisterInfo::isPhysicalRegister(DestReg)) {
DestReg = RI.getSubReg(DestReg, SubIdx);
DestReg = TRI->getSubReg(DestReg, SubIdx);
SubIdx = 0;
}

3
lib/Target/X86/X86InstrInfo.h
View File

@ -482,7 +482,8 @@ public:
AliasAnalysis *AA) const;
void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SubIdx,
const MachineInstr *Orig) const;
const MachineInstr *Orig,
const TargetRegisterInfo *TRI) const;
/// convertToThreeAddress - This method must be implemented by targets that
/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target

3
test/CodeGen/ARM/2009-11-07-SubRegAsmPrinting.ll
View File

@ -1,5 +1,6 @@
; RUN: llc -mcpu=cortex-a8 < %s | FileCheck %s
; XFAIL: *
; PR5423
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
target triple = "armv7-eabi"