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reduce indentation by using continue, no functionality change.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121662 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2010-12-13 01:11:17 +00:00
parent eac8f35da8
commit d5b4db9824
1 changed files with 39 additions and 36 deletions
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21
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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@ -637,13 +637,17 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
}
Chain = P.getValue(1);
Parts[i] = P;
// If the source register was virtual and if we know something about it,
// add an assert node.
if (TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) &&
RegisterVT.isInteger() && !RegisterVT.isVector()) {
if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) ||
!RegisterVT.isInteger() || RegisterVT.isVector())
continue;
unsigned SlotNo = Regs[Part+i]-TargetRegisterInfo::FirstVirtualRegister;
if (FuncInfo.LiveOutRegInfo.size() > SlotNo) {
if (SlotNo >= FuncInfo.LiveOutRegInfo.size()) continue;
const FunctionLoweringInfo::LiveOutInfo &LOI =
FuncInfo.LiveOutRegInfo[SlotNo];
@ -671,15 +675,14 @@ SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG,
isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
else if (NumZeroBits >= RegSize-32)
isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
else
continue;
if (FromVT != MVT::Other)
P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
// Add an assertion node.
assert(FromVT != MVT::Other);
Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
RegisterVT, P, DAG.getValueType(FromVT));
}
}
Parts[i] = P;
}
Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(),
NumRegs, RegisterVT, ValueVT);