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llvm_report_error already prints "LLVM ERROR:". So stop reporting errors like "LLVM ERROR: llvm: error:" or "LLVM ERROR: ERROR:".

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77971 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer
2009-08-03 13:33:33 +00:00
parent 0144280cfb
commit d5fe92efbc
5 changed files with 9 additions and 10 deletions
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2
include/llvm/Target/TargetData.h
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@ -112,7 +112,7 @@ public:
/// @note This has to exist, because this is a pass, but it should never be /// @note This has to exist, because this is a pass, but it should never be
/// used. /// used.
TargetData() : ImmutablePass(&ID) { TargetData() : ImmutablePass(&ID) {
llvm_report_error("ERROR: Bad TargetData ctor used. " llvm_report_error("Bad TargetData ctor used. "
"Tool did not specify a TargetData to use?"); "Tool did not specify a TargetData to use?");
} }

11
lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
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@ -5074,7 +5074,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
Input.ConstraintVT.isInteger()) || Input.ConstraintVT.isInteger()) ||
(OpInfo.ConstraintVT.getSizeInBits() != (OpInfo.ConstraintVT.getSizeInBits() !=
Input.ConstraintVT.getSizeInBits())) { Input.ConstraintVT.getSizeInBits())) {
llvm_report_error("llvm: error: Unsupported asm: input constraint" llvm_report_error("Unsupported asm: input constraint"
" with a matching output constraint of incompatible" " with a matching output constraint of incompatible"
" type!"); " type!");
} }
@ -5179,7 +5179,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
// Copy the output from the appropriate register. Find a register that // Copy the output from the appropriate register. Find a register that
// we can use. // we can use.
if (OpInfo.AssignedRegs.Regs.empty()) { if (OpInfo.AssignedRegs.Regs.empty()) {
llvm_report_error("llvm: error: Couldn't allocate output reg for" llvm_report_error("Couldn't allocate output reg for"
" constraint '" + OpInfo.ConstraintCode + "'!"); " constraint '" + OpInfo.ConstraintCode + "'!");
} }
@ -5233,8 +5233,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
|| (OpFlag & 7) == 6 /* EARLYCLOBBER REGDEF */) { || (OpFlag & 7) == 6 /* EARLYCLOBBER REGDEF */) {
// Add (OpFlag&0xffff)>>3 registers to MatchedRegs. // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
if (OpInfo.isIndirect) { if (OpInfo.isIndirect) {
llvm_report_error("llvm: error: " llvm_report_error("Don't know how to handle tied indirect "
"Don't know how to handle tied indirect "
"register inputs yet!"); "register inputs yet!");
} }
RegsForValue MatchedRegs; RegsForValue MatchedRegs;
@ -5277,7 +5276,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0], TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode[0],
hasMemory, Ops, DAG); hasMemory, Ops, DAG);
if (Ops.empty()) { if (Ops.empty()) {
llvm_report_error("llvm: error: Invalid operand for inline asm" llvm_report_error("Invalid operand for inline asm"
" constraint '" + OpInfo.ConstraintCode + "'!"); " constraint '" + OpInfo.ConstraintCode + "'!");
} }
@ -5308,7 +5307,7 @@ void SelectionDAGLowering::visitInlineAsm(CallSite CS) {
// Copy the input into the appropriate registers. // Copy the input into the appropriate registers.
if (OpInfo.AssignedRegs.Regs.empty()) { if (OpInfo.AssignedRegs.Regs.empty()) {
llvm_report_error("llvm: error: Couldn't allocate input reg for" llvm_report_error("Couldn't allocate input reg for"
" constraint '"+ OpInfo.ConstraintCode +"'!"); " constraint '"+ OpInfo.ConstraintCode +"'!");
} }

2
lib/ExecutionEngine/Interpreter/Execution.cpp
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@ -644,7 +644,7 @@ void Interpreter::visitUnwindInst(UnwindInst &I) {
} }
void Interpreter::visitUnreachableInst(UnreachableInst &I) { void Interpreter::visitUnreachableInst(UnreachableInst &I) {
llvm_report_error("ERROR: Program executed an 'unreachable' instruction!"); llvm_report_error("Program executed an 'unreachable' instruction!");
} }
void Interpreter::visitBranchInst(BranchInst &I) { void Interpreter::visitBranchInst(BranchInst &I) {

2
lib/ExecutionEngine/JIT/Intercept.cpp
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@ -141,7 +141,7 @@ void *JIT::getPointerToNamedFunction(const std::string &Name,
return RP; return RP;
if (AbortOnFailure) { if (AbortOnFailure) {
llvm_report_error("ERROR: Program used external function '"+Name+ llvm_report_error("Program used external function '"+Name+
"' which could not be resolved!"); "' which could not be resolved!");
} }
return 0; return 0;

2
lib/Target/ARM/ARMCodeEmitter.cpp
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@ -749,7 +749,7 @@ void Emitter<CodeEmitter>::emitDataProcessingInstruction(
const TargetInstrDesc &TID = MI.getDesc(); const TargetInstrDesc &TID = MI.getDesc();
if (TID.Opcode == ARM::BFC) { if (TID.Opcode == ARM::BFC) {
llvm_report_error("ERROR: ARMv6t2 JIT is not yet supported."); llvm_report_error("ARMv6t2 JIT is not yet supported.");
} }
// Part of binary is determined by TableGn. // Part of binary is determined by TableGn.