6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-04-05 01:31:05 +00:00
Code Issues Projects Releases Wiki Activity

Add ARM fast-isel support for materializing the address of a global in cases where the global uses an indirect symbol.

Browse Source 
rdar://9431157



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132522 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eli Friedman 2011-06-03 01:13:19 +00:00
parent c5d93bb5c8
commit d6412c940e
2 changed files with 44 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
lib/Target/ARM/ARMFastISel.cpp
View File

@ -577,9 +577,6 @@ unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
Reloc::Model RelocM = TM.getRelocationModel();
// TODO: No external globals for now.
if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) return 0;
// TODO: Need more magic for ARM PIC.
if (!isThumb && (RelocM == Reloc::PIC_)) return 0;
@ -614,6 +611,23 @@ unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
.addImm(0);
}
AddOptionalDefs(MIB);
if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) {
unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
if (isThumb)
MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::t2LDRi12),
NewDestReg)
.addReg(DestReg)
.addImm(0);
else
MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRi12),
NewDestReg)
.addReg(DestReg)
.addImm(0);
DestReg = NewDestReg;
AddOptionalDefs(MIB);
}
return DestReg;
}

28
test/CodeGen/ARM/fast-isel.ll
View File

@ -131,4 +131,30 @@ bb3:
; ARM: sxth
; ARM: add
; ARM: sub
}
}
; Check loads/stores with globals
@test4g = external global i32
define void @test4() {
%a = load i32* @test4g
%b = add i32 %a, 1
store i32 %b, i32* @test4g
ret void
; THUMB: ldr.n r0, LCPI4_1
; THUMB: ldr r0, [r0]
; THUMB: ldr r0, [r0]
; THUMB: adds r0, #1
; THUMB: ldr.n r1, LCPI4_0
; THUMB: ldr r1, [r1]
; THUMB: str r0, [r1]
; ARM: ldr r0, LCPI4_1
; ARM: ldr r0, [r0]
; ARM: ldr r0, [r0]
; ARM: add r0, r0, #1
; ARM: ldr r1, LCPI4_0
; ARM: ldr r1, [r1]
; ARM: str r0, [r1]
}