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PowerPC: Remove LDrs pattern.

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The LDrs pattern is a duplicate of LD, except that it accepts memory
addresses where the displacement is a symbolLo64.  An operand type
"memrs" is defined for just that purpose.

However, this wouldn't be necessary if the default "memrix" operand
type were to simply accept 64-bit symbolic addresses directly.
The only problem with that is that it uses "symbolLo", which is
hardcoded to 32-bit.

To fix this, this commit changes "memri" and "memrix" to use new
operand types for the memory displacement, which allow iPTR
instead of i32.  This will also make address parsing easier to
implment in the asm parser.

No change in generated code.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178005 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ulrich Weigand
2013-03-26 10:55:45 +00:00
parent 2b0850b830
commit d67768db80
3 changed files with 9 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
lib/Target/PowerPC/PPCAsmPrinter.cpp
View File

@ -458,11 +458,10 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
// Transform %Xd = LDtocL <ga:@sym>, %Xs // Transform %Xd = LDtocL <ga:@sym>, %Xs
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin()); LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());
// Change the opcode to LDrs, which is a form of LD with the offset // Change the opcode to LD. If the global address is external, has
// specified by a SymbolLo. If the global address is external, has
// common linkage, or is a jump table address, then reference the // common linkage, or is a jump table address, then reference the
// associated TOC entry. Otherwise reference the symbol directly. // associated TOC entry. Otherwise reference the symbol directly.
TmpInst.setOpcode(PPC::LDrs); TmpInst.setOpcode(PPC::LD);
const MachineOperand &MO = MI->getOperand(1); const MachineOperand &MO = MI->getOperand(1);
assert((MO.isGlobal() || MO.isJTI() || MO.isCPI()) && assert((MO.isGlobal() || MO.isJTI() || MO.isCPI()) &&
"Invalid operand for LDtocL!"); "Invalid operand for LDtocL!");
@ -548,9 +547,8 @@ void PPCAsmPrinter::EmitInstruction(const MachineInstr *MI) {
// Transform %Xd = LDgotTprelL <ga:@sym>, %Xs // Transform %Xd = LDgotTprelL <ga:@sym>, %Xs
LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin()); LowerPPCMachineInstrToMCInst(MI, TmpInst, *this, Subtarget.isDarwin());
// Change the opcode to LDrs, which is a form of LD with the offset // Change the opcode to LD.
// specified by a SymbolLo. TmpInst.setOpcode(PPC::LD);
TmpInst.setOpcode(PPC::LDrs);
const MachineOperand &MO = MI->getOperand(1); const MachineOperand &MO = MI->getOperand(1);
const GlobalValue *GValue = MO.getGlobal(); const GlobalValue *GValue = MO.getGlobal();
MCSymbol *MOSymbol = Mang->getSymbol(GValue); MCSymbol *MOSymbol = Mang->getSymbol(GValue);

8
lib/Target/PowerPC/PPCInstr64Bit.td
View File

@ -32,11 +32,6 @@ def symbolLo64 : Operand<i64> {
def tocentry : Operand<iPTR> { def tocentry : Operand<iPTR> {
let MIOperandInfo = (ops i64imm:$imm); let MIOperandInfo = (ops i64imm:$imm);
} }
def memrs : Operand<iPTR> { // memri where the immediate is a symbolLo64
let PrintMethod = "printMemRegImm";
let EncoderMethod = "getMemRIXEncoding";
let MIOperandInfo = (ops symbolLo64:$off, ptr_rc_nor0:$reg);
}
def tlsreg : Operand<i64> { def tlsreg : Operand<i64> {
let EncoderMethod = "getTLSRegEncoding"; let EncoderMethod = "getTLSRegEncoding";
} }
@ -626,9 +621,6 @@ let canFoldAsLoad = 1, PPC970_Unit = 2 in {
def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src), def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src),
"ld $rD, $src", LdStLD, "ld $rD, $src", LdStLD,
[(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64; [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
def LDrs : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrs:$src),
"ld $rD, $src", LdStLD,
[]>, isPPC64;
// The following three definitions are selected for small code model only. // The following three definitions are selected for small code model only.
// Otherwise, we need to create two instructions to form a 32-bit offset, // Otherwise, we need to create two instructions to form a 32-bit offset,
// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().

7
lib/Target/PowerPC/PPCInstrInfo.td
View File

@ -375,9 +375,12 @@ def crbitm: Operand<i8> {
// A version of ptr_rc which excludes R0 (or X0 in 64-bit mode). // A version of ptr_rc which excludes R0 (or X0 in 64-bit mode).
def ptr_rc_nor0 : PointerLikeRegClass<1>; def ptr_rc_nor0 : PointerLikeRegClass<1>;
def dispRI : Operand<iPTR>;
def dispRIX : Operand<iPTR>;
def memri : Operand<iPTR> { def memri : Operand<iPTR> {
let PrintMethod = "printMemRegImm"; let PrintMethod = "printMemRegImm";
let MIOperandInfo = (ops symbolLo:$imm, ptr_rc_nor0:$reg); let MIOperandInfo = (ops dispRI:$imm, ptr_rc_nor0:$reg);
let EncoderMethod = "getMemRIEncoding"; let EncoderMethod = "getMemRIEncoding";
} }
def memrr : Operand<iPTR> { def memrr : Operand<iPTR> {
@ -386,7 +389,7 @@ def memrr : Operand<iPTR> {
} }
def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits. def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
let PrintMethod = "printMemRegImmShifted"; let PrintMethod = "printMemRegImmShifted";
let MIOperandInfo = (ops symbolLo:$imm, ptr_rc_nor0:$reg); let MIOperandInfo = (ops dispRIX:$imm, ptr_rc_nor0:$reg);
let EncoderMethod = "getMemRIXEncoding"; let EncoderMethod = "getMemRIXEncoding";
} }