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Disable rematerialization in TwoAddressInstructionPass.
It is redundant; RegisterCoalescer will do the remat if it can't eliminate the copy. Collected instruction counts before and after this. A few extra instructions are generated due to spilling but it is normal to see these kinds of changes with almost any small codegen change, according to Jakob. This also fixed rdar://11830760 where xor is expected instead of movi0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160749 91177308-0d34-0410-b5e6-96231b3b80d8
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Manman Ren
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9f14ed1c60
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@ -55,7 +55,6 @@ STATISTIC(NumCommuted , "Number of instructions commuted to coalesce");
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STATISTIC(NumAggrCommuted , "Number of instructions aggressively commuted");
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STATISTIC(NumConvertedTo3Addr, "Number of instructions promoted to 3-address");
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STATISTIC(Num3AddrSunk, "Number of 3-address instructions sunk");
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STATISTIC(NumReMats, "Number of instructions re-materialized");
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STATISTIC(NumDeletes, "Number of dead instructions deleted");
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STATISTIC(NumReSchedUps, "Number of instructions re-scheduled up");
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STATISTIC(NumReSchedDowns, "Number of instructions re-scheduled down");
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@ -92,10 +91,6 @@ namespace {
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unsigned Reg,
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MachineBasicBlock::iterator OldPos);
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bool isProfitableToReMat(unsigned Reg, const TargetRegisterClass *RC,
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MachineInstr *MI, MachineInstr *DefMI,
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MachineBasicBlock *MBB, unsigned Loc);
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bool NoUseAfterLastDef(unsigned Reg, MachineBasicBlock *MBB, unsigned Dist,
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unsigned &LastDef);
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@ -301,55 +296,6 @@ bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB,
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return true;
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}
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/// isTwoAddrUse - Return true if the specified MI is using the specified
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/// register as a two-address operand.
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static bool isTwoAddrUse(MachineInstr *UseMI, unsigned Reg) {
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const MCInstrDesc &MCID = UseMI->getDesc();
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for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
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MachineOperand &MO = UseMI->getOperand(i);
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if (MO.isReg() && MO.getReg() == Reg &&
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(MO.isDef() || UseMI->isRegTiedToDefOperand(i)))
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// Earlier use is a two-address one.
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return true;
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}
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return false;
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}
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/// isProfitableToReMat - Return true if the heuristics determines it is likely
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/// to be profitable to re-materialize the definition of Reg rather than copy
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/// the register.
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bool
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TwoAddressInstructionPass::isProfitableToReMat(unsigned Reg,
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const TargetRegisterClass *RC,
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MachineInstr *MI, MachineInstr *DefMI,
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MachineBasicBlock *MBB, unsigned Loc) {
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bool OtherUse = false;
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for (MachineRegisterInfo::use_nodbg_iterator UI = MRI->use_nodbg_begin(Reg),
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UE = MRI->use_nodbg_end(); UI != UE; ++UI) {
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MachineOperand &UseMO = UI.getOperand();
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MachineInstr *UseMI = UseMO.getParent();
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MachineBasicBlock *UseMBB = UseMI->getParent();
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if (UseMBB == MBB) {
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DenseMap<MachineInstr*, unsigned>::iterator DI = DistanceMap.find(UseMI);
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if (DI != DistanceMap.end() && DI->second == Loc)
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continue; // Current use.
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OtherUse = true;
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// There is at least one other use in the MBB that will clobber the
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// register.
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if (isTwoAddrUse(UseMI, Reg))
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return true;
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}
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}
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// If other uses in MBB are not two-address uses, then don't remat.
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if (OtherUse)
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return false;
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// No other uses in the same block, remat if it's defined in the same
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// block so it does not unnecessarily extend the live range.
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return MBB == DefMI->getParent();
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}
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/// NoUseAfterLastDef - Return true if there are no intervening uses between the
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/// last instruction in the MBB that defines the specified register and the
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/// two-address instruction which is being processed. It also returns the last
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@ -538,7 +484,7 @@ regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
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}
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/// isProfitableToReMat - Return true if it's potentially profitable to commute
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/// isProfitableToCommute - Return true if it's potentially profitable to commute
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/// the two-address instruction that's being processed.
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bool
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TwoAddressInstructionPass::isProfitableToCommute(unsigned regA, unsigned regB,
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@ -1518,26 +1464,9 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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mi->getOperand(i).getReg() != regA);
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#endif
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// Emit a copy or rematerialize the definition.
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bool isCopy = false;
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const TargetRegisterClass *rc = MRI->getRegClass(regB);
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MachineInstr *DefMI = MRI->getUniqueVRegDef(regB);
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// If it's safe and profitable, remat the definition instead of
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// copying it.
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if (DefMI &&
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DefMI->isAsCheapAsAMove() &&
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DefMI->isSafeToReMat(TII, AA, regB) &&
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isProfitableToReMat(regB, rc, mi, DefMI, mbbi, Dist)){
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DEBUG(dbgs() << "2addr: REMATTING : " << *DefMI << "\n");
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unsigned regASubIdx = mi->getOperand(DstIdx).getSubReg();
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TII->reMaterialize(*mbbi, mi, regA, regASubIdx, DefMI, *TRI);
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ReMatRegs.set(TargetRegisterInfo::virtReg2Index(regB));
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++NumReMats;
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} else {
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BuildMI(*mbbi, mi, mi->getDebugLoc(), TII->get(TargetOpcode::COPY),
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regA).addReg(regB);
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isCopy = true;
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}
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// Emit a copy.
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BuildMI(*mbbi, mi, mi->getDebugLoc(), TII->get(TargetOpcode::COPY),
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regA).addReg(regB);
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// Update DistanceMap.
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MachineBasicBlock::iterator prevMI = prior(mi);
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@ -1561,9 +1490,8 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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MO.setReg(regA);
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if (isCopy)
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// Propagate SrcRegMap.
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SrcRegMap[regA] = regB;
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// Propagate SrcRegMap.
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SrcRegMap[regA] = regB;
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}
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if (AllUsesCopied) {
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@ -4,8 +4,8 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
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define i32 @test1(i32 %x, i32 %n, i32 %w, i32* %vp) nounwind readnone {
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entry:
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; CHECK: test1:
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; CHECK: btl
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; CHECK-NEXT: movl $12, %eax
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; CHECK: movl $12, %eax
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; CHECK-NEXT: btl
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; CHECK-NEXT: cmovael (%rcx), %eax
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; CHECK-NEXT: ret
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@ -19,8 +19,8 @@ entry:
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define i32 @test2(i32 %x, i32 %n, i32 %w, i32* %vp) nounwind readnone {
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entry:
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; CHECK: test2:
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; CHECK: btl
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; CHECK-NEXT: movl $12, %eax
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; CHECK: movl $12, %eax
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; CHECK-NEXT: btl
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; CHECK-NEXT: cmovbl (%rcx), %eax
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; CHECK-NEXT: ret
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@ -142,6 +142,7 @@ if.else:
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define i32 @l4(i32 %a, i32 %b) nounwind {
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entry:
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; CHECK: l4:
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; CHECK: xor
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; CHECK: sub
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; CHECK-NOT: cmp
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%cmp = icmp sgt i32 %b, %a
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@ -189,8 +189,8 @@ entry:
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%call = tail call noalias i8* @_Znam(i64 %D) nounwind noredzone
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ret i8* %call
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; CHECK: test12:
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; CHECK: mulq
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; CHECK: movq $-1, %rdi
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; CHECK: mulq
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; CHECK: cmovnoq %rax, %rdi
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; CHECK: jmp __Znam
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}
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