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Allow physregs to occur in the dag with multiple types. Though I don't like

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this, it is a requirement on PPC, which can have an f32 value in r3 at one
point in a function and a f64 value in r3 at another point.  :(


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23160 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-08-30 22:38:05 +00:00
parent 2ea0c66ae5
commit d6a80778e5
1 changed files with 1 additions and 1 deletions
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2
include/llvm/CodeGen/SelectionDAG.h
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@ -355,7 +355,7 @@ private:
std::map<std::pair<unsigned, std::pair<SDOperand, SDOperand> >,
SDNode *> BinaryOps;
std::vector<RegisterSDNode*> RegNodes;
std::map<std::pair<unsigned, MVT::ValueType>, RegisterSDNode*> RegNodes;
std::vector<CondCodeSDNode*> CondCodeNodes;
std::map<std::pair<SDOperand, std::pair<SDOperand, MVT::ValueType> >,