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Use SubRegIndex in SystemZ.

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Anton, please review the change to SystemZAsmPrinter.cpp. It could be a bug.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104515 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2010-05-24 17:43:01 +00:00
parent fff916a960
commit d6be874e8c
3 changed files with 10 additions and 17 deletions
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4
lib/Target/SystemZ/AsmPrinter/SystemZAsmPrinter.cpp
View File

@ -124,9 +124,9 @@ void SystemZAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
unsigned Reg = MO.getReg();
if (Modifier && strncmp(Modifier, "subreg", 6) == 0) {
if (strncmp(Modifier + 7, "even", 4) == 0)
Reg = TM.getRegisterInfo()->getSubReg(Reg, SystemZ::SUBREG_EVEN);
Reg = TM.getRegisterInfo()->getSubReg(Reg, SystemZ::subreg_even32);
else if (strncmp(Modifier + 7, "odd", 3) == 0)
Reg = TM.getRegisterInfo()->getSubReg(Reg, SystemZ::SUBREG_ODD);
Reg = TM.getRegisterInfo()->getSubReg(Reg, SystemZ::subreg_odd32);
else
assert(0 && "Invalid subreg modifier");
}

11
lib/Target/SystemZ/SystemZRegisterInfo.h
View File

@ -1,4 +1,4 @@
//===- SystemZRegisterInfo.h - SystemZ Register Information Impl ----*- C++ -*-===//
//===-- SystemZRegisterInfo.h - SystemZ Register Information ----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
@ -19,15 +19,6 @@
namespace llvm {
namespace SystemZ {
/// SubregIndex - The index of various sized subregister classes. Note that
/// these indices must be kept in sync with the class indices in the
/// SystemZRegisterInfo.td file.
enum SubregIndex {
SUBREG_32BIT = 1, SUBREG_EVEN = 1, SUBREG_ODD = 2
};
}
class SystemZSubtarget;
class SystemZInstrInfo;
class Type;

12
lib/Target/SystemZ/SystemZRegisterInfo.td
View File

@ -145,11 +145,13 @@ def F15L : FPRL<15, "f15", [F15S]>, DwarfRegNum<[31]>;
// Status register
def PSW : SystemZReg<"psw">;
def subreg_32bit : PatLeaf<(i32 1)>;
def subreg_even32 : PatLeaf<(i32 1)>;
def subreg_odd32 : PatLeaf<(i32 2)>;
def subreg_even : PatLeaf<(i32 3)>;
def subreg_odd : PatLeaf<(i32 4)>;
let Namespace = "SystemZ" in {
def subreg_32bit : SubRegIndex { let NumberHack = 1; }
def subreg_even32 : SubRegIndex { let NumberHack = 1; }
def subreg_odd32 : SubRegIndex { let NumberHack = 2; }
def subreg_even : SubRegIndex { let NumberHack = 3; }
def subreg_odd : SubRegIndex { let NumberHack = 4; }
}
def : SubRegSet<1, [R0D, R1D, R2D, R3D, R4D, R5D, R6D, R7D,
R8D, R9D, R10D, R11D, R12D, R13D, R14D, R15D],