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Better error-handling for DisassembleThumb2DPSoReg() where the 3-reg operand

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instructions should have Rd (Inst{11-8}) != 0b1111.

Ref: A6.3 32-bit Thumb instruction encoding
     A6.3.11 Data-processing (shifted register)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101788 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2010-04-19 17:16:40 +00:00
parent 17192a1dd8
commit d6cc53cfe4
1 changed files with 6 additions and 3 deletions
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9
lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
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@ -1340,12 +1340,15 @@ static bool DisassembleThumb2DPSoReg(MCInst &MI, unsigned Opcode, uint32_t insn,
if ((Idx = TID.getOperandConstraint(OpIdx, TOI::TIED_TO)) != -1) {
// Process tied_to operand constraint.
MI.addOperand(MI.getOperand(Idx));
} else {
assert(!NoDstReg && "Internal error");
++OpIdx;
} else if (!NoDstReg) {
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
decodeRn(insn))));
++OpIdx;
} else {
DEBUG(errs() << "Thumb encoding error: d==15 for three-reg operands.\n");
return false;
}
++OpIdx;
}
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,