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[Hexagon] Adding missing instruction encodings and tests.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227495 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2015-01-29 21:30:22 +00:00
parent d742d5db60
commit d6ce18cdf9
4 changed files with 160 additions and 41 deletions
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2
lib/Target/Hexagon/HexagonInstrInfo.td
View File

@ -91,9 +91,11 @@ class T_CMP <string mnemonic, bits<2> MajOp, bit isNot, Operand ImmOp>
let Inst{1-0} = dst;
}
let isCodeGenOnly = 0 in {
def C2_cmpeqi : T_CMP <"cmp.eq", 0b00, 0, s10Ext>;
def C2_cmpgti : T_CMP <"cmp.gt", 0b01, 0, s10Ext>;
def C2_cmpgtui : T_CMP <"cmp.gtu", 0b10, 0, u9Ext>;
}
class T_CMP_pat <InstHexagon MI, PatFrag OpNode, PatLeaf ImmPred>
: Pat<(i1 (OpNode (i32 IntRegs:$src1), ImmPred:$src2)),

55
lib/Target/Hexagon/HexagonInstrInfoV4.td
View File

@ -2663,45 +2663,30 @@ let Predicates = [HasV4T, UseMEMOP] in {
// incorrect code for negative numbers.
// Pd=cmpb.eq(Rs,#u8)
let isCompare = 1, isExtendable = 1, opExtendable = 2, hasSideEffects = 0,
validSubTargets = HasV4SubT in
class CMP_NOT_REG_IMM<string OpName, bits<2> op, Operand ImmOp,
list<dag> Pattern>
: ALU32Inst <(outs PredRegs:$dst), (ins IntRegs:$src1, ImmOp:$src2),
"$dst = !cmp."#OpName#"($src1, #$src2)",
Pattern,
"", ALU32_2op_tc_2early_SLOT0123> {
bits<2> dst;
bits<5> src1;
bits<10> src2;
let IClass = 0b0111;
let Inst{27-24} = 0b0101;
let Inst{23-22} = op;
let Inst{20-16} = src1;
let Inst{21} = !if (!eq(OpName, "gtu"), 0b0, src2{9});
let Inst{13-5} = src2{8-0};
let Inst{4-2} = 0b100;
let Inst{1-0} = dst;
// p=!cmp.eq(r1,#s10)
let isCodeGenOnly = 0 in {
def C4_cmpneqi : T_CMP <"cmp.eq", 0b00, 1, s10Ext>;
def C4_cmpltei : T_CMP <"cmp.gt", 0b01, 1, s10Ext>;
def C4_cmplteui : T_CMP <"cmp.gtu", 0b10, 1, u9Ext>;
}
let opExtentBits = 10, isExtentSigned = 1 in {
def C4_cmpneqi : CMP_NOT_REG_IMM <"eq", 0b00, s10Ext, [(set (i1 PredRegs:$dst),
(setne (i32 IntRegs:$src1), s10ExtPred:$src2))]>;
def : T_CMP_pat <C4_cmpneqi, setne, s10ExtPred>;
def : T_CMP_pat <C4_cmpltei, setle, s10ExtPred>;
def : T_CMP_pat <C4_cmplteui, setule, u9ImmPred>;
def C4_cmpltei : CMP_NOT_REG_IMM <"gt", 0b01, s10Ext, [(set (i1 PredRegs:$dst),
(not (setgt (i32 IntRegs:$src1), s10ExtPred:$src2)))]>;
// rs <= rt -> !(rs > rt).
/*
def: Pat<(i1 (setle (i32 IntRegs:$src1), s10ExtPred:$src2)),
(C2_not (C2_cmpgti IntRegs:$src1, s10ExtPred:$src2))>;
// (C4_cmpltei IntRegs:$src1, s10ExtPred:$src2)>;
*/
// Map cmplt(Rs, Imm) -> !cmpgt(Rs, Imm-1).
def: Pat<(i1 (setlt (i32 IntRegs:$src1), s8ExtPred:$src2)),
(C4_cmpltei IntRegs:$src1, (DEC_CONST_SIGNED s8ExtPred:$src2))>;
}
let opExtentBits = 9 in
def C4_cmplteui : CMP_NOT_REG_IMM <"gtu", 0b10, u9Ext, [(set (i1 PredRegs:$dst),
(not (setugt (i32 IntRegs:$src1), u9ExtPred:$src2)))]>;
def : Pat <(brcond (i1 (setne (and (i32 IntRegs:$src1), 255), u8ImmPred:$src2)),
bb:$offset),
(J2_jumpf (A4_cmpbeqi (i32 IntRegs:$src1), u8ImmPred:$src2),
bb:$offset)>,
Requires<[HasV4T]>;
// rs != rt -> !(rs == rt).
def: Pat<(i1 (setne (i32 IntRegs:$src1), s10ExtPred:$src2)),
(C4_cmpneqi IntRegs:$src1, s10ExtPred:$src2)>;
// SDNode for converting immediate C to C-1.
def DEC_CONST_BYTE : SDNodeXForm<imm, [{

8
test/MC/Disassembler/Hexagon/alu32_perm.txt
View File

@ -1,5 +1,7 @@
# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
# Hexagon Programmer's Reference Manual 11.1.2 ALU32/PERM
# Combine words in to doublewords
0x11 0xdf 0x95 0xf3
# CHECK: r17 = combine(r31.h, r21.h)
0x11 0xdf 0xb5 0xf3
@ -16,6 +18,8 @@
# CHECK: r17:16 = combine(r21, #31)
0x10 0xdf 0x15 0xf5
# CHECK: r17:16 = combine(r21, r31)
# Mux
0xf1 0xc3 0x75 0x73
# CHECK: r17 = mux(p3, r21, #31)
0xb1 0xc2 0xff 0x73
@ -24,9 +28,13 @@
# CHECK: r17 = mux(p3, #21, #31)
0x71 0xdf 0x15 0xf4
# CHECK: r17 = mux(p3, r21, r31)
# Shift word by 16
0x11 0xc0 0x15 0x70
# CHECK: r17 = aslh(r21)
0x11 0xc0 0x35 0x70
# CHECK: r17 = asrh(r21)
# Pack high and low halfwords
0x10 0xdf 0x95 0xf5
# CHECK: r17:16 = packhl(r21, r31)

136
test/MC/Disassembler/Hexagon/alu32_pred.txt
View File

@ -1,11 +1,51 @@
# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
# Hexagon Programmer's Reference Manual 11.1.3 ALU32/PRED
# Conditional add
0xf1 0xc3 0x75 0x74
# CHECK: if (p3) r17 = add(r21, #31)
0x03 0x40 0x45 0x85 0xf1 0xe3 0x75 0x74
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) r17 = add(r21, #31)
0xf1 0xc3 0xf5 0x74
# CHECK: if (!p3) r17 = add(r21, #31)
0x03 0x40 0x45 0x85 0xf1 0xe3 0xf5 0x74
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = add(r21, #31)
0x71 0xdf 0x15 0xfb
# CHECK: if (p3) r17 = add(r21, r31)
0x03 0x40 0x45 0x85 0x71 0xff 0x15 0xfb
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) r17 = add(r21, r31)
0xf1 0xdf 0x15 0xfb
# CHECK: if (!p3) r17 = add(r21, r31)
0x03 0x40 0x45 0x85 0xf1 0xff 0x15 0xfb
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = add(r21, r31)
# Conditional shift halfword
0x11 0xe3 0x15 0x70
# CHECK: if (p3) r17 = aslh(r21)
0x03 0x40 0x45 0x85 0x11 0xe7 0x15 0x70
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) r17 = aslh(r21)
0x11 0xeb 0x15 0x70
# CHECK: if (!p3) r17 = aslh(r21)
0x03 0x40 0x45 0x85 0x11 0xef 0x15 0x70
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = aslh(r21)
0x11 0xe3 0x35 0x70
# CHECK: if (p3) r17 = asrh(r21)
0x03 0x40 0x45 0x85 0x11 0xe7 0x35 0x70
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) r17 = asrh(r21)
0x11 0xeb 0x35 0x70
# CHECK: if (!p3) r17 = asrh(r21)
0x03 0x40 0x45 0x85 0x11 0xef 0x35 0x70
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = asrh(r21)
# Conditional combine
0x70 0xdf 0x15 0xfd
# CHECK: if (p3) r17:16 = combine(r21, r31)
0xf0 0xdf 0x15 0xfd
@ -16,24 +56,74 @@
0x03 0x40 0x45 0x85 0xf0 0xff 0x15 0xfd
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17:16 = combine(r21, r31)
0x03 0x40 0x45 0x85 0x70 0xff 0x15 0xfd
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) r17:16 = combine(r21, r31)
0x03 0x40 0x45 0x85 0xf0 0xff 0x15 0xfd
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17:16 = combine(r21, r31)
# Conditional logical operations
0x71 0xdf 0x15 0xf9
# CHECK: if (p3) r17 = and(r21, r31)
0xf1 0xdf 0x15 0xf9
# CHECK: if (!p3) r17 = and(r21, r31)
0x03 0x40 0x45 0x85 0x71 0xff 0x15 0xf9
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) r17 = and(r21, r31)
0x03 0x40 0x45 0x85 0xf1 0xff 0x15 0xf9
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = and(r21, r31)
0x71 0xdf 0x35 0xf9
# CHECK: if (p3) r17 = or(r21, r31)
0xf1 0xdf 0x35 0xf9
# CHECK: if (!p3) r17 = or(r21, r31)
0x03 0x40 0x45 0x85 0x71 0xff 0x35 0xf9
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) r17 = or(r21, r31)
0x03 0x40 0x45 0x85 0xf1 0xff 0x35 0xf9
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = or(r21, r31)
0x71 0xdf 0x75 0xf9
# CHECK: if (p3) r17 = xor(r21, r31)
0xf1 0xdf 0x75 0xf9
# CHECK: if (!p3) r17 = xor(r21, r31)
0x03 0x40 0x45 0x85 0x71 0xff 0x75 0xf9
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) r17 = xor(r21, r31)
0x03 0x40 0x45 0x85 0xf1 0xff 0x75 0xf9
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = xor(r21, r31)
# Conditional subtract
0x71 0xdf 0x35 0xfb
# CHECK: if (p3) r17 = sub(r31, r21)
0xf1 0xdf 0x35 0xfb
# CHECK: if (!p3) r17 = sub(r31, r21)
0x03 0x40 0x45 0x85 0x71 0xff 0x35 0xfb
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) r17 = sub(r31, r21)
0x03 0x40 0x45 0x85 0xf1 0xff 0x35 0xfb
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = sub(r31, r21)
# Conditional sign extend
0x11 0xe3 0xb5 0x70
# CHECK: if (p3) r17 = sxtb(r21)
0x11 0xeb 0xb5 0x70
# CHECK: if (!p3) r17 = sxtb(r21)
0x03 0x40 0x45 0x85 0x11 0xe7 0xb5 0x70
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) r17 = sxtb(r21)
0x03 0x40 0x45 0x85 0x11 0xef 0xb5 0x70
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = sxtb(r21)
0x11 0xe3 0xf5 0x70
# CHECK: if (p3) r17 = sxth(r21)
0x11 0xeb 0xf5 0x70
# CHECK: if (!p3) r17 = sxth(r21)
0x03 0x40 0x45 0x85 0x11 0xe7 0xf5 0x70
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) r17 = sxth(r21)
0x03 0x40 0x45 0x85 0x11 0xef 0xf5 0x70
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = sxth(r21)
# Conditional transfer
0xb1 0xc2 0x60 0x7e
# CHECK: if (p3) r17 = #21
0xb1 0xc2 0xe0 0x7e
@ -44,10 +134,42 @@
0x03 0x40 0x45 0x85 0xb1 0xe2 0xe0 0x7e
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = #21
# Conditional zero extend
0x11 0xe3 0x95 0x70
# CHECK: if (p3) r17 = zxtb(r21)
0x11 0xeb 0x95 0x70
# CHECK: if (!p3) r17 = zxtb(r21)
0x03 0x40 0x45 0x85 0x11 0xe7 0x95 0x70
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) r17 = zxtb(r21)
0x03 0x40 0x45 0x85 0x11 0xef 0x95 0x70
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = zxtb(r21)
0x11 0xe3 0xd5 0x70
# CHECK: if (p3) r17 = zxth(r21)
0x11 0xeb 0xd5 0x70
# CHECK: if (!p3) r17 = zxth(r21)
0x03 0x40 0x45 0x85 0x11 0xe7 0xd5 0x70
# CHECK: p3 = r5
# CHECK-NEXT: if (p3.new) r17 = zxth(r21)
0x03 0x40 0x45 0x85 0x11 0xef 0xd5 0x70
# CHECK: p3 = r5
# CHECK-NEXT: if (!p3.new) r17 = zxth(r21)
# Compare
0xe3 0xc3 0x15 0x75
# CHECK: p3 = cmp.eq(r21, #31)
0xf3 0xc3 0x15 0x75
# CHECK: p3 = !cmp.eq(r21, #31)
0xe3 0xc3 0x55 0x75
# CHECK: p3 = cmp.gt(r21, #31)
0xf3 0xc3 0x55 0x75
# CHECK: p3 = !cmp.gt(r21, #31)
0xe3 0xc3 0x95 0x75
# CHECK: p3 = cmp.gtu(r21, #31)
0xf3 0xc3 0x95 0x75
# CHECK: p3 = !cmp.gtu(r21, #31)
0x03 0xdf 0x15 0xf2
# CHECK: p3 = cmp.eq(r21, r31)
0x13 0xdf 0x15 0xf2
@ -60,6 +182,8 @@
# CHECK: p3 = cmp.gtu(r21, r31)
0x13 0xdf 0x75 0xf2
# CHECK: p3 = !cmp.gtu(r21, r31)
# Compare to general register
0xf1 0xe3 0x55 0x73
# CHECK: r17 = cmp.eq(r21, #31)
0xf1 0xe3 0x75 0x73