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ARM has to provide its own TargetLowering::findRepresentativeClass because its scalar floating point registers alias its vector registers.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108761 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2010-07-19 22:15:08 +00:00
parent bd3c63c70e
commit d70f57b254
4 changed files with 33 additions and 12 deletions
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12
include/llvm/Target/TargetLowering.h
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@@ -993,6 +993,11 @@ protected:
Synthesizable[VT.getSimpleVT().SimpleTy] = isSynthesizable;
}
/// findRepresentativeClass - Return the largest legal super-reg register class
/// of the specified register class.
virtual const TargetRegisterClass *
findRepresentativeClass(const TargetRegisterClass *RC) const;
/// computeRegisterProperties - Once all of the register classes are added,
/// this allows us to compute derived properties we expose.
void computeRegisterProperties();
@@ -1698,12 +1703,7 @@ private:
/// hasLegalSuperRegRegClasses - Return true if the specified register class
/// has one or more super-reg register classes that are legal.
bool hasLegalSuperRegRegClasses(const TargetRegisterClass *RC);
/// findRepresentativeClass - Return the largest legal super-reg register class
/// of the specified register class.
const TargetRegisterClass *
findRepresentativeClass(const TargetRegisterClass *RC);
bool hasLegalSuperRegRegClasses(const TargetRegisterClass *RC) const;
};
/// GetReturnInfo - Given an LLVM IR type and return type attributes,