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Switch the MachineOperand accessors back to the short names like

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isReg, etc., from isRegister, etc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57006 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
2008-10-03 15:45:36 +00:00
parent 06a62886fb
commit d735b8019b
71 changed files with 538 additions and 530 deletions
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4
lib/CodeGen/RegAllocSimple.cpp
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@ -190,7 +190,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
MachineOperand &MO = MI->getOperand(i);
if (MO.isRegister() && MO.getReg() &&
if (MO.isReg() && MO.getReg() &&
TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
unsigned virtualReg = (unsigned) MO.getReg();
DOUT << "op: " << MO << "\n";
@ -209,7 +209,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
// must be same register number as the source operand that is
// tied to. This maps a = b + c into b = b + c, and saves b into
// a's spot.
assert(MI->getOperand(TiedOp).isRegister() &&
assert(MI->getOperand(TiedOp).isReg() &&
MI->getOperand(TiedOp).getReg() &&
MI->getOperand(TiedOp).isUse() &&
"Two address instruction invalid!");