6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-11-01 00:17:01 +00:00
Code Issues Projects Releases Wiki Activity

R600/SI: 64-bit and larger memory access must be at least 4-byte aligned

Browse Source 
This is true for SI only. CI+ supports unaligned memory accesses,
but this requires driver support, so for now we disallow unaligned
accesses for all GCN targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227822 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
2015-02-02 18:02:28 +00:00
parent 80e70ee18e
commit d73d1062fe
3 changed files with 80 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
lib/Target/R600/SIISelLowering.cpp
View File

@@ -315,9 +315,8 @@ bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
if (!VT.isSimple() || VT == MVT::Other)
return false;
// XXX - CI changes say "Support for unaligned memory accesses" but I don't
// see what for specifically. The wording everywhere else seems to be the
// same.
// TODO - CI+ supports unaligned memory accesses, but this requires driver
// support.
// XXX - The only mention I see of this in the ISA manual is for LDS direct
// reads the "byte address and must be dword aligned". Is it also true for the
@@ -334,7 +333,8 @@ bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
// This applies to private, global, and constant memory.
if (IsFast)
*IsFast = true;
return VT.bitsGT(MVT::i32);
return VT.bitsGT(MVT::i32) && Align % 4 == 0;
}
EVT SITargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,