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https://github.com/c64scene-ar/llvm-6502.git
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[Hexagon] Adding alu vector instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227493 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu
parent
26c81cc870
commit
d742d5db60
@ -183,10 +183,27 @@ class T_ALU32_3op_sfx<string mnemonic, string suffix, bits<3> MajOp,
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let AsmString = "$Rd = "#mnemonic#"($Rs, $Rt)"#suffix;
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}
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let isCodeGenOnly = 0 in {
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def A2_svaddh : T_ALU32_3op<"vaddh", 0b110, 0b000, 0, 1>;
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def A2_svsubh : T_ALU32_3op<"vsubh", 0b110, 0b100, 1, 0>;
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}
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let Defs = [USR_OVF], Itinerary = ALU32_3op_tc_2_SLOT0123,
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isCodeGenOnly = 0 in {
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def A2_svaddhs : T_ALU32_3op_sfx<"vaddh", ":sat", 0b110, 0b001, 0, 1>;
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def A2_addsat : T_ALU32_3op_sfx<"add", ":sat", 0b110, 0b010, 0, 1>;
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def A2_svadduhs : T_ALU32_3op_sfx<"vadduh", ":sat", 0b110, 0b011, 0, 1>;
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def A2_svsubhs : T_ALU32_3op_sfx<"vsubh", ":sat", 0b110, 0b101, 1, 0>;
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def A2_subsat : T_ALU32_3op_sfx<"sub", ":sat", 0b110, 0b110, 1, 0>;
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def A2_svsubuhs : T_ALU32_3op_sfx<"vsubuh", ":sat", 0b110, 0b111, 1, 0>;
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}
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let Itinerary = ALU32_3op_tc_2_SLOT0123, isCodeGenOnly = 0 in
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def A2_svavghs : T_ALU32_3op_sfx<"vavgh", ":rnd", 0b111, 0b001, 0, 1>;
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let isCodeGenOnly = 0 in {
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def A2_svavgh : T_ALU32_3op<"vavgh", 0b111, 0b000, 0, 1>;
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def A2_svnavgh : T_ALU32_3op<"vnavgh", 0b111, 0b011, 1, 0>;
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}
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multiclass T_ALU32_3op_p<string mnemonic, bits<3> MajOp, bits<3> MinOp,
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@ -333,7 +350,7 @@ def A2_combineii: ALU32Inst <(outs DoubleRegs:$Rdd), (ins s8Ext:$s8, s8Imm:$S8),
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//===----------------------------------------------------------------------===//
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// Template class for predicated ADD of a reg and an Immediate value.
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//===----------------------------------------------------------------------===//
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let hasNewValue = 1 in
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let hasNewValue = 1, hasSideEffects = 0 in
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class T_Addri_Pred <bit PredNot, bit PredNew>
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: ALU32_ri <(outs IntRegs:$Rd),
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(ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8),
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@ -359,7 +376,7 @@ class T_Addri_Pred <bit PredNot, bit PredNew>
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//===----------------------------------------------------------------------===//
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// A2_addi: Add a signed immediate to a register.
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//===----------------------------------------------------------------------===//
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let hasNewValue = 1 in
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let hasNewValue = 1, hasSideEffects = 0 in
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class T_Addri <Operand immOp, list<dag> pattern = [] >
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: ALU32_ri <(outs IntRegs:$Rd),
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(ins IntRegs:$Rs, immOp:$s16),
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@ -829,6 +846,163 @@ def: Pat<(sra I32:$src1, (i32 16)), (A2_asrh I32:$src1)>;
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def: Pat<(sext_inreg I32:$src1, i8), (A2_sxtb I32:$src1)>;
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def: Pat<(sext_inreg I32:$src1, i16), (A2_sxth I32:$src1)>;
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//===----------------------------------------------------------------------===//
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// Template class for vector add and avg
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//===----------------------------------------------------------------------===//
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class T_VectALU_64 <string opc, bits<3> majOp, bits<3> minOp,
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bit isSat, bit isRnd, bit isCrnd, bit SwapOps >
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: ALU64_rr < (outs DoubleRegs:$Rdd),
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(ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
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"$Rdd = "#opc#"($Rss, $Rtt)"#!if(isRnd, ":rnd", "")
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#!if(isCrnd,":crnd","")
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#!if(isSat, ":sat", ""),
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[], "", ALU64_tc_2_SLOT23 > {
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bits<5> Rdd;
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bits<5> Rss;
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bits<5> Rtt;
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let IClass = 0b1101;
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let Inst{27-24} = 0b0011;
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let Inst{23-21} = majOp;
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let Inst{20-16} = !if (SwapOps, Rtt, Rss);
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let Inst{12-8} = !if (SwapOps, Rss, Rtt);
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let Inst{7-5} = minOp;
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let Inst{4-0} = Rdd;
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}
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// ALU64 - Vector add
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// Rdd=vadd[u][bhw](Rss,Rtt)
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let Itinerary = ALU64_tc_1_SLOT23 in {
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def A2_vaddub : T_VectALU_64 < "vaddub", 0b000, 0b000, 0, 0, 0, 0>;
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def A2_vaddh : T_VectALU_64 < "vaddh", 0b000, 0b010, 0, 0, 0, 0>;
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def A2_vaddw : T_VectALU_64 < "vaddw", 0b000, 0b101, 0, 0, 0, 0>;
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}
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// Rdd=vadd[u][bhw](Rss,Rtt):sat
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let Defs = [USR_OVF] in {
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def A2_vaddubs : T_VectALU_64 < "vaddub", 0b000, 0b001, 1, 0, 0, 0>;
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def A2_vaddhs : T_VectALU_64 < "vaddh", 0b000, 0b011, 1, 0, 0, 0>;
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def A2_vadduhs : T_VectALU_64 < "vadduh", 0b000, 0b100, 1, 0, 0, 0>;
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def A2_vaddws : T_VectALU_64 < "vaddw", 0b000, 0b110, 1, 0, 0, 0>;
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}
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// ALU64 - Vector average
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// Rdd=vavg[u][bhw](Rss,Rtt)
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let Itinerary = ALU64_tc_1_SLOT23 in {
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def A2_vavgub : T_VectALU_64 < "vavgub", 0b010, 0b000, 0, 0, 0, 0>;
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def A2_vavgh : T_VectALU_64 < "vavgh", 0b010, 0b010, 0, 0, 0, 0>;
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def A2_vavguh : T_VectALU_64 < "vavguh", 0b010, 0b101, 0, 0, 0, 0>;
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def A2_vavgw : T_VectALU_64 < "vavgw", 0b011, 0b000, 0, 0, 0, 0>;
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def A2_vavguw : T_VectALU_64 < "vavguw", 0b011, 0b011, 0, 0, 0, 0>;
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}
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// Rdd=vavg[u][bhw](Rss,Rtt)[:rnd|:crnd]
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def A2_vavgubr : T_VectALU_64 < "vavgub", 0b010, 0b001, 0, 1, 0, 0>;
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def A2_vavghr : T_VectALU_64 < "vavgh", 0b010, 0b011, 0, 1, 0, 0>;
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def A2_vavghcr : T_VectALU_64 < "vavgh", 0b010, 0b100, 0, 0, 1, 0>;
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def A2_vavguhr : T_VectALU_64 < "vavguh", 0b010, 0b110, 0, 1, 0, 0>;
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def A2_vavgwr : T_VectALU_64 < "vavgw", 0b011, 0b001, 0, 1, 0, 0>;
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def A2_vavgwcr : T_VectALU_64 < "vavgw", 0b011, 0b010, 0, 0, 1, 0>;
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def A2_vavguwr : T_VectALU_64 < "vavguw", 0b011, 0b100, 0, 1, 0, 0>;
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// Rdd=vnavg[bh](Rss,Rtt)
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let Itinerary = ALU64_tc_1_SLOT23 in {
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def A2_vnavgh : T_VectALU_64 < "vnavgh", 0b100, 0b000, 0, 0, 0, 1>;
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def A2_vnavgw : T_VectALU_64 < "vnavgw", 0b100, 0b011, 0, 0, 0, 1>;
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}
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// Rdd=vnavg[bh](Rss,Rtt)[:rnd|:crnd]:sat
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let Defs = [USR_OVF] in {
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def A2_vnavghr : T_VectALU_64 < "vnavgh", 0b100, 0b001, 1, 1, 0, 1>;
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def A2_vnavghcr : T_VectALU_64 < "vnavgh", 0b100, 0b010, 1, 0, 1, 1>;
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def A2_vnavgwr : T_VectALU_64 < "vnavgw", 0b100, 0b100, 1, 1, 0, 1>;
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def A2_vnavgwcr : T_VectALU_64 < "vnavgw", 0b100, 0b110, 1, 0, 1, 1>;
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}
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// Rdd=vsub[u][bh](Rss,Rtt)
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let Itinerary = ALU64_tc_1_SLOT23 in {
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def A2_vsubub : T_VectALU_64 < "vsubub", 0b001, 0b000, 0, 0, 0, 1>;
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def A2_vsubh : T_VectALU_64 < "vsubh", 0b001, 0b010, 0, 0, 0, 1>;
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def A2_vsubw : T_VectALU_64 < "vsubw", 0b001, 0b101, 0, 0, 0, 1>;
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}
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// Rdd=vsub[u][bh](Rss,Rtt):sat
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let Defs = [USR_OVF] in {
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def A2_vsububs : T_VectALU_64 < "vsubub", 0b001, 0b001, 1, 0, 0, 1>;
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def A2_vsubhs : T_VectALU_64 < "vsubh", 0b001, 0b011, 1, 0, 0, 1>;
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def A2_vsubuhs : T_VectALU_64 < "vsubuh", 0b001, 0b100, 1, 0, 0, 1>;
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def A2_vsubws : T_VectALU_64 < "vsubw", 0b001, 0b110, 1, 0, 0, 1>;
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}
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// Rdd=vmax[u][bhw](Rss,Rtt)
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def A2_vmaxb : T_VectALU_64 < "vmaxb", 0b110, 0b110, 0, 0, 0, 1>;
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def A2_vmaxub : T_VectALU_64 < "vmaxub", 0b110, 0b000, 0, 0, 0, 1>;
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def A2_vmaxh : T_VectALU_64 < "vmaxh", 0b110, 0b001, 0, 0, 0, 1>;
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def A2_vmaxuh : T_VectALU_64 < "vmaxuh", 0b110, 0b010, 0, 0, 0, 1>;
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def A2_vmaxw : T_VectALU_64 < "vmaxw", 0b110, 0b011, 0, 0, 0, 1>;
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def A2_vmaxuw : T_VectALU_64 < "vmaxuw", 0b101, 0b101, 0, 0, 0, 1>;
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// Rdd=vmin[u][bhw](Rss,Rtt)
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def A2_vminb : T_VectALU_64 < "vminb", 0b110, 0b111, 0, 0, 0, 1>;
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def A2_vminub : T_VectALU_64 < "vminub", 0b101, 0b000, 0, 0, 0, 1>;
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def A2_vminh : T_VectALU_64 < "vminh", 0b101, 0b001, 0, 0, 0, 1>;
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def A2_vminuh : T_VectALU_64 < "vminuh", 0b101, 0b010, 0, 0, 0, 1>;
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def A2_vminw : T_VectALU_64 < "vminw", 0b101, 0b011, 0, 0, 0, 1>;
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def A2_vminuw : T_VectALU_64 < "vminuw", 0b101, 0b100, 0, 0, 0, 1>;
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//===----------------------------------------------------------------------===//
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// Template class for vector compare
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//===----------------------------------------------------------------------===//
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let hasSideEffects = 0 in
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class T_vcmp <string Str, bits<4> minOp>
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: ALU64_rr <(outs PredRegs:$Pd),
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(ins DoubleRegs:$Rss, DoubleRegs:$Rtt),
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"$Pd = "#Str#"($Rss, $Rtt)", [],
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"", ALU64_tc_2early_SLOT23> {
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bits<2> Pd;
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bits<5> Rss;
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bits<5> Rtt;
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let IClass = 0b1101;
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let Inst{27-23} = 0b00100;
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let Inst{13} = minOp{3};
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let Inst{7-5} = minOp{2-0};
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let Inst{1-0} = Pd;
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let Inst{20-16} = Rss;
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let Inst{12-8} = Rtt;
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}
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class T_vcmp_pat<InstHexagon MI, PatFrag Op, ValueType T>
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: Pat<(i1 (Op (T DoubleRegs:$Rss), (T DoubleRegs:$Rtt))),
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(i1 (MI DoubleRegs:$Rss, DoubleRegs:$Rtt))>;
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// Vector compare bytes
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def A2_vcmpbeq : T_vcmp <"vcmpb.eq", 0b0110>;
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def A2_vcmpbgtu : T_vcmp <"vcmpb.gtu", 0b0111>;
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// Vector compare halfwords
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def A2_vcmpheq : T_vcmp <"vcmph.eq", 0b0011>;
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def A2_vcmphgt : T_vcmp <"vcmph.gt", 0b0100>;
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def A2_vcmphgtu : T_vcmp <"vcmph.gtu", 0b0101>;
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// Vector compare words
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def A2_vcmpweq : T_vcmp <"vcmpw.eq", 0b0000>;
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def A2_vcmpwgt : T_vcmp <"vcmpw.gt", 0b0001>;
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def A2_vcmpwgtu : T_vcmp <"vcmpw.gtu", 0b0010>;
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def: T_vcmp_pat<A2_vcmpbeq, seteq, v8i8>;
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def: T_vcmp_pat<A2_vcmpbgtu, setugt, v8i8>;
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def: T_vcmp_pat<A2_vcmpheq, seteq, v4i16>;
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def: T_vcmp_pat<A2_vcmphgt, setgt, v4i16>;
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def: T_vcmp_pat<A2_vcmphgtu, setugt, v4i16>;
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def: T_vcmp_pat<A2_vcmpweq, seteq, v2i32>;
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def: T_vcmp_pat<A2_vcmpwgt, setgt, v2i32>;
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def: T_vcmp_pat<A2_vcmpwgtu, setugt, v2i32>;
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//===----------------------------------------------------------------------===//
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// ALU32/PERM -
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//===----------------------------------------------------------------------===//
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@ -169,7 +169,7 @@ def IntRegs : RegisterClass<"Hexagon", [i32,f32], 32,
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R10, R11, R29, R30, R31)> {
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}
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def DoubleRegs : RegisterClass<"Hexagon", [i64,f64], 64,
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def DoubleRegs : RegisterClass<"Hexagon", [i64, f64, v8i8, v4i16, v2i32], 64,
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(add (sequence "D%u", 0, 4),
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(sequence "D%u", 6, 13), D5, D14, D15)>;
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@ -1,11 +1,15 @@
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# RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s
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# Hexagon Programmer's Reference Manual 11.1.1 ALU32/ALU
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# Add
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0xf1 0xc3 0x15 0xb0
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# CHECK: r17 = add(r21, #31)
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0x11 0xdf 0x15 0xf3
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# CHECK: r17 = add(r21, r31)
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0x11 0xdf 0x55 0xf6
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# CHECK: r17 = add(r21, r31):sat
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# And
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0xf1 0xc3 0x15 0x76
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# CHECK: r17 = and(r21, #31)
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0xf1 0xc3 0x95 0x76
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@ -20,16 +24,24 @@
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# CHECK: r17 = and(r21, ~r31)
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0x11 0xd5 0xbf 0xf1
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# CHECK: r17 = or(r21, ~r31)
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# Nop
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0x00 0xc0 0x00 0x7f
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# CHECK: nop
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# Subtract
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0xb1 0xc2 0x5f 0x76
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# CHECK: r17 = sub(#21, r31)
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0x11 0xdf 0x35 0xf3
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# CHECK: r17 = sub(r31, r21)
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0x11 0xdf 0xd5 0xf6
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# CHECK: r17 = sub(r31, r21):sat
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# Sign extend
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0x11 0xc0 0xbf 0x70
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# CHECK: r17 = sxtb(r31)
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# Transfer immediate
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0x15 0xc0 0x31 0x72
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# CHECK: r17.h = #21
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0x15 0xc0 0x31 0x71
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@ -38,7 +50,35 @@
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# CHECK: r17 = #32767
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0xf1 0xff 0xdf 0x78
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# CHECK: r17 = ##65535
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# Transfer register
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0x11 0xc0 0x75 0x70
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# CHECK: r17 = r21
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# Vector add halfwords
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0x11 0xdf 0x15 0xf6
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# CHECK: r17 = vaddh(r21, r31)
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0x11 0xdf 0x35 0xf6
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# CHECK: r17 = vaddh(r21, r31):sat
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0x11 0xdf 0x75 0xf6
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# CHECK: r17 = vadduh(r21, r31):sat
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# Vector average halfwords
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0x11 0xdf 0x15 0xf7
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# CHECK: r17 = vavgh(r21, r31)
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0x11 0xdf 0x35 0xf7
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# CHECK: r17 = vavgh(r21, r31):rnd
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0x11 0xdf 0x75 0xf7
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# CHECK: r17 = vnavgh(r31, r21)
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# Vector subtract halfwords
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0x11 0xdf 0x95 0xf6
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# CHECK: r17 = vsubh(r31, r21)
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0x11 0xdf 0xb5 0xf6
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# CHECK: r17 = vsubh(r31, r21):sat
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0x11 0xdf 0xf5 0xf6
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# CHECK: r17 = vsubuh(r31, r21):sat
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# Zero extend
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0x11 0xc0 0xd5 0x70
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# CHECK: r17 = zxth(r21)
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