From d742d5db60805fb627cc1ee52e6e38e217ff9922 Mon Sep 17 00:00:00 2001 From: Colin LeMahieu Date: Thu, 29 Jan 2015 21:09:30 +0000 Subject: [PATCH] [Hexagon] Adding alu vector instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@227493 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/Hexagon/HexagonInstrInfo.td | 178 ++++++++++++++++++++- lib/Target/Hexagon/HexagonRegisterInfo.td | 2 +- test/MC/Disassembler/Hexagon/alu32_alu.txt | 40 +++++ 3 files changed, 217 insertions(+), 3 deletions(-) diff --git a/lib/Target/Hexagon/HexagonInstrInfo.td b/lib/Target/Hexagon/HexagonInstrInfo.td index 727bc2c034d..447ba095561 100644 --- a/lib/Target/Hexagon/HexagonInstrInfo.td +++ b/lib/Target/Hexagon/HexagonInstrInfo.td @@ -183,10 +183,27 @@ class T_ALU32_3op_sfx MajOp, let AsmString = "$Rd = "#mnemonic#"($Rs, $Rt)"#suffix; } +let isCodeGenOnly = 0 in { +def A2_svaddh : T_ALU32_3op<"vaddh", 0b110, 0b000, 0, 1>; +def A2_svsubh : T_ALU32_3op<"vsubh", 0b110, 0b100, 1, 0>; +} + let Defs = [USR_OVF], Itinerary = ALU32_3op_tc_2_SLOT0123, isCodeGenOnly = 0 in { + def A2_svaddhs : T_ALU32_3op_sfx<"vaddh", ":sat", 0b110, 0b001, 0, 1>; def A2_addsat : T_ALU32_3op_sfx<"add", ":sat", 0b110, 0b010, 0, 1>; + def A2_svadduhs : T_ALU32_3op_sfx<"vadduh", ":sat", 0b110, 0b011, 0, 1>; + def A2_svsubhs : T_ALU32_3op_sfx<"vsubh", ":sat", 0b110, 0b101, 1, 0>; def A2_subsat : T_ALU32_3op_sfx<"sub", ":sat", 0b110, 0b110, 1, 0>; + def A2_svsubuhs : T_ALU32_3op_sfx<"vsubuh", ":sat", 0b110, 0b111, 1, 0>; +} + +let Itinerary = ALU32_3op_tc_2_SLOT0123, isCodeGenOnly = 0 in +def A2_svavghs : T_ALU32_3op_sfx<"vavgh", ":rnd", 0b111, 0b001, 0, 1>; + +let isCodeGenOnly = 0 in { +def A2_svavgh : T_ALU32_3op<"vavgh", 0b111, 0b000, 0, 1>; +def A2_svnavgh : T_ALU32_3op<"vnavgh", 0b111, 0b011, 1, 0>; } multiclass T_ALU32_3op_p MajOp, bits<3> MinOp, @@ -333,7 +350,7 @@ def A2_combineii: ALU32Inst <(outs DoubleRegs:$Rdd), (ins s8Ext:$s8, s8Imm:$S8), //===----------------------------------------------------------------------===// // Template class for predicated ADD of a reg and an Immediate value. //===----------------------------------------------------------------------===// -let hasNewValue = 1 in +let hasNewValue = 1, hasSideEffects = 0 in class T_Addri_Pred : ALU32_ri <(outs IntRegs:$Rd), (ins PredRegs:$Pu, IntRegs:$Rs, s8Ext:$s8), @@ -359,7 +376,7 @@ class T_Addri_Pred //===----------------------------------------------------------------------===// // A2_addi: Add a signed immediate to a register. //===----------------------------------------------------------------------===// -let hasNewValue = 1 in +let hasNewValue = 1, hasSideEffects = 0 in class T_Addri pattern = [] > : ALU32_ri <(outs IntRegs:$Rd), (ins IntRegs:$Rs, immOp:$s16), @@ -829,6 +846,163 @@ def: Pat<(sra I32:$src1, (i32 16)), (A2_asrh I32:$src1)>; def: Pat<(sext_inreg I32:$src1, i8), (A2_sxtb I32:$src1)>; def: Pat<(sext_inreg I32:$src1, i16), (A2_sxth I32:$src1)>; +//===----------------------------------------------------------------------===// +// Template class for vector add and avg +//===----------------------------------------------------------------------===// + +class T_VectALU_64 majOp, bits<3> minOp, + bit isSat, bit isRnd, bit isCrnd, bit SwapOps > + : ALU64_rr < (outs DoubleRegs:$Rdd), + (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), + "$Rdd = "#opc#"($Rss, $Rtt)"#!if(isRnd, ":rnd", "") + #!if(isCrnd,":crnd","") + #!if(isSat, ":sat", ""), + [], "", ALU64_tc_2_SLOT23 > { + bits<5> Rdd; + bits<5> Rss; + bits<5> Rtt; + + let IClass = 0b1101; + + let Inst{27-24} = 0b0011; + let Inst{23-21} = majOp; + let Inst{20-16} = !if (SwapOps, Rtt, Rss); + let Inst{12-8} = !if (SwapOps, Rss, Rtt); + let Inst{7-5} = minOp; + let Inst{4-0} = Rdd; + } + +// ALU64 - Vector add +// Rdd=vadd[u][bhw](Rss,Rtt) +let Itinerary = ALU64_tc_1_SLOT23 in { + def A2_vaddub : T_VectALU_64 < "vaddub", 0b000, 0b000, 0, 0, 0, 0>; + def A2_vaddh : T_VectALU_64 < "vaddh", 0b000, 0b010, 0, 0, 0, 0>; + def A2_vaddw : T_VectALU_64 < "vaddw", 0b000, 0b101, 0, 0, 0, 0>; +} + +// Rdd=vadd[u][bhw](Rss,Rtt):sat +let Defs = [USR_OVF] in { + def A2_vaddubs : T_VectALU_64 < "vaddub", 0b000, 0b001, 1, 0, 0, 0>; + def A2_vaddhs : T_VectALU_64 < "vaddh", 0b000, 0b011, 1, 0, 0, 0>; + def A2_vadduhs : T_VectALU_64 < "vadduh", 0b000, 0b100, 1, 0, 0, 0>; + def A2_vaddws : T_VectALU_64 < "vaddw", 0b000, 0b110, 1, 0, 0, 0>; +} + +// ALU64 - Vector average +// Rdd=vavg[u][bhw](Rss,Rtt) +let Itinerary = ALU64_tc_1_SLOT23 in { + def A2_vavgub : T_VectALU_64 < "vavgub", 0b010, 0b000, 0, 0, 0, 0>; + def A2_vavgh : T_VectALU_64 < "vavgh", 0b010, 0b010, 0, 0, 0, 0>; + def A2_vavguh : T_VectALU_64 < "vavguh", 0b010, 0b101, 0, 0, 0, 0>; + def A2_vavgw : T_VectALU_64 < "vavgw", 0b011, 0b000, 0, 0, 0, 0>; + def A2_vavguw : T_VectALU_64 < "vavguw", 0b011, 0b011, 0, 0, 0, 0>; +} + +// Rdd=vavg[u][bhw](Rss,Rtt)[:rnd|:crnd] +def A2_vavgubr : T_VectALU_64 < "vavgub", 0b010, 0b001, 0, 1, 0, 0>; +def A2_vavghr : T_VectALU_64 < "vavgh", 0b010, 0b011, 0, 1, 0, 0>; +def A2_vavghcr : T_VectALU_64 < "vavgh", 0b010, 0b100, 0, 0, 1, 0>; +def A2_vavguhr : T_VectALU_64 < "vavguh", 0b010, 0b110, 0, 1, 0, 0>; + +def A2_vavgwr : T_VectALU_64 < "vavgw", 0b011, 0b001, 0, 1, 0, 0>; +def A2_vavgwcr : T_VectALU_64 < "vavgw", 0b011, 0b010, 0, 0, 1, 0>; +def A2_vavguwr : T_VectALU_64 < "vavguw", 0b011, 0b100, 0, 1, 0, 0>; + +// Rdd=vnavg[bh](Rss,Rtt) +let Itinerary = ALU64_tc_1_SLOT23 in { + def A2_vnavgh : T_VectALU_64 < "vnavgh", 0b100, 0b000, 0, 0, 0, 1>; + def A2_vnavgw : T_VectALU_64 < "vnavgw", 0b100, 0b011, 0, 0, 0, 1>; +} + +// Rdd=vnavg[bh](Rss,Rtt)[:rnd|:crnd]:sat +let Defs = [USR_OVF] in { + def A2_vnavghr : T_VectALU_64 < "vnavgh", 0b100, 0b001, 1, 1, 0, 1>; + def A2_vnavghcr : T_VectALU_64 < "vnavgh", 0b100, 0b010, 1, 0, 1, 1>; + def A2_vnavgwr : T_VectALU_64 < "vnavgw", 0b100, 0b100, 1, 1, 0, 1>; + def A2_vnavgwcr : T_VectALU_64 < "vnavgw", 0b100, 0b110, 1, 0, 1, 1>; +} + +// Rdd=vsub[u][bh](Rss,Rtt) +let Itinerary = ALU64_tc_1_SLOT23 in { + def A2_vsubub : T_VectALU_64 < "vsubub", 0b001, 0b000, 0, 0, 0, 1>; + def A2_vsubh : T_VectALU_64 < "vsubh", 0b001, 0b010, 0, 0, 0, 1>; + def A2_vsubw : T_VectALU_64 < "vsubw", 0b001, 0b101, 0, 0, 0, 1>; +} + +// Rdd=vsub[u][bh](Rss,Rtt):sat +let Defs = [USR_OVF] in { + def A2_vsububs : T_VectALU_64 < "vsubub", 0b001, 0b001, 1, 0, 0, 1>; + def A2_vsubhs : T_VectALU_64 < "vsubh", 0b001, 0b011, 1, 0, 0, 1>; + def A2_vsubuhs : T_VectALU_64 < "vsubuh", 0b001, 0b100, 1, 0, 0, 1>; + def A2_vsubws : T_VectALU_64 < "vsubw", 0b001, 0b110, 1, 0, 0, 1>; +} + +// Rdd=vmax[u][bhw](Rss,Rtt) +def A2_vmaxb : T_VectALU_64 < "vmaxb", 0b110, 0b110, 0, 0, 0, 1>; +def A2_vmaxub : T_VectALU_64 < "vmaxub", 0b110, 0b000, 0, 0, 0, 1>; +def A2_vmaxh : T_VectALU_64 < "vmaxh", 0b110, 0b001, 0, 0, 0, 1>; +def A2_vmaxuh : T_VectALU_64 < "vmaxuh", 0b110, 0b010, 0, 0, 0, 1>; +def A2_vmaxw : T_VectALU_64 < "vmaxw", 0b110, 0b011, 0, 0, 0, 1>; +def A2_vmaxuw : T_VectALU_64 < "vmaxuw", 0b101, 0b101, 0, 0, 0, 1>; + +// Rdd=vmin[u][bhw](Rss,Rtt) +def A2_vminb : T_VectALU_64 < "vminb", 0b110, 0b111, 0, 0, 0, 1>; +def A2_vminub : T_VectALU_64 < "vminub", 0b101, 0b000, 0, 0, 0, 1>; +def A2_vminh : T_VectALU_64 < "vminh", 0b101, 0b001, 0, 0, 0, 1>; +def A2_vminuh : T_VectALU_64 < "vminuh", 0b101, 0b010, 0, 0, 0, 1>; +def A2_vminw : T_VectALU_64 < "vminw", 0b101, 0b011, 0, 0, 0, 1>; +def A2_vminuw : T_VectALU_64 < "vminuw", 0b101, 0b100, 0, 0, 0, 1>; + +//===----------------------------------------------------------------------===// +// Template class for vector compare +//===----------------------------------------------------------------------===// +let hasSideEffects = 0 in +class T_vcmp minOp> + : ALU64_rr <(outs PredRegs:$Pd), + (ins DoubleRegs:$Rss, DoubleRegs:$Rtt), + "$Pd = "#Str#"($Rss, $Rtt)", [], + "", ALU64_tc_2early_SLOT23> { + bits<2> Pd; + bits<5> Rss; + bits<5> Rtt; + + let IClass = 0b1101; + + let Inst{27-23} = 0b00100; + let Inst{13} = minOp{3}; + let Inst{7-5} = minOp{2-0}; + let Inst{1-0} = Pd; + let Inst{20-16} = Rss; + let Inst{12-8} = Rtt; + } + +class T_vcmp_pat + : Pat<(i1 (Op (T DoubleRegs:$Rss), (T DoubleRegs:$Rtt))), + (i1 (MI DoubleRegs:$Rss, DoubleRegs:$Rtt))>; + +// Vector compare bytes +def A2_vcmpbeq : T_vcmp <"vcmpb.eq", 0b0110>; +def A2_vcmpbgtu : T_vcmp <"vcmpb.gtu", 0b0111>; + +// Vector compare halfwords +def A2_vcmpheq : T_vcmp <"vcmph.eq", 0b0011>; +def A2_vcmphgt : T_vcmp <"vcmph.gt", 0b0100>; +def A2_vcmphgtu : T_vcmp <"vcmph.gtu", 0b0101>; + +// Vector compare words +def A2_vcmpweq : T_vcmp <"vcmpw.eq", 0b0000>; +def A2_vcmpwgt : T_vcmp <"vcmpw.gt", 0b0001>; +def A2_vcmpwgtu : T_vcmp <"vcmpw.gtu", 0b0010>; + +def: T_vcmp_pat; +def: T_vcmp_pat; +def: T_vcmp_pat; +def: T_vcmp_pat; +def: T_vcmp_pat; +def: T_vcmp_pat; +def: T_vcmp_pat; +def: T_vcmp_pat; + //===----------------------------------------------------------------------===// // ALU32/PERM - //===----------------------------------------------------------------------===// diff --git a/lib/Target/Hexagon/HexagonRegisterInfo.td b/lib/Target/Hexagon/HexagonRegisterInfo.td index 4d98eacb930..fc4e7158455 100644 --- a/lib/Target/Hexagon/HexagonRegisterInfo.td +++ b/lib/Target/Hexagon/HexagonRegisterInfo.td @@ -169,7 +169,7 @@ def IntRegs : RegisterClass<"Hexagon", [i32,f32], 32, R10, R11, R29, R30, R31)> { } -def DoubleRegs : RegisterClass<"Hexagon", [i64,f64], 64, +def DoubleRegs : RegisterClass<"Hexagon", [i64, f64, v8i8, v4i16, v2i32], 64, (add (sequence "D%u", 0, 4), (sequence "D%u", 6, 13), D5, D14, D15)>; diff --git a/test/MC/Disassembler/Hexagon/alu32_alu.txt b/test/MC/Disassembler/Hexagon/alu32_alu.txt index 7fd40077929..42dc373ac05 100644 --- a/test/MC/Disassembler/Hexagon/alu32_alu.txt +++ b/test/MC/Disassembler/Hexagon/alu32_alu.txt @@ -1,11 +1,15 @@ # RUN: llvm-mc --triple hexagon -disassemble < %s | FileCheck %s +# Hexagon Programmer's Reference Manual 11.1.1 ALU32/ALU +# Add 0xf1 0xc3 0x15 0xb0 # CHECK: r17 = add(r21, #31) 0x11 0xdf 0x15 0xf3 # CHECK: r17 = add(r21, r31) 0x11 0xdf 0x55 0xf6 # CHECK: r17 = add(r21, r31):sat + +# And 0xf1 0xc3 0x15 0x76 # CHECK: r17 = and(r21, #31) 0xf1 0xc3 0x95 0x76 @@ -20,16 +24,24 @@ # CHECK: r17 = and(r21, ~r31) 0x11 0xd5 0xbf 0xf1 # CHECK: r17 = or(r21, ~r31) + +# Nop 0x00 0xc0 0x00 0x7f # CHECK: nop + +# Subtract 0xb1 0xc2 0x5f 0x76 # CHECK: r17 = sub(#21, r31) 0x11 0xdf 0x35 0xf3 # CHECK: r17 = sub(r31, r21) 0x11 0xdf 0xd5 0xf6 # CHECK: r17 = sub(r31, r21):sat + +# Sign extend 0x11 0xc0 0xbf 0x70 # CHECK: r17 = sxtb(r31) + +# Transfer immediate 0x15 0xc0 0x31 0x72 # CHECK: r17.h = #21 0x15 0xc0 0x31 0x71 @@ -38,7 +50,35 @@ # CHECK: r17 = #32767 0xf1 0xff 0xdf 0x78 # CHECK: r17 = ##65535 + +# Transfer register 0x11 0xc0 0x75 0x70 # CHECK: r17 = r21 + +# Vector add halfwords +0x11 0xdf 0x15 0xf6 +# CHECK: r17 = vaddh(r21, r31) +0x11 0xdf 0x35 0xf6 +# CHECK: r17 = vaddh(r21, r31):sat +0x11 0xdf 0x75 0xf6 +# CHECK: r17 = vadduh(r21, r31):sat + +# Vector average halfwords +0x11 0xdf 0x15 0xf7 +# CHECK: r17 = vavgh(r21, r31) +0x11 0xdf 0x35 0xf7 +# CHECK: r17 = vavgh(r21, r31):rnd +0x11 0xdf 0x75 0xf7 +# CHECK: r17 = vnavgh(r31, r21) + +# Vector subtract halfwords +0x11 0xdf 0x95 0xf6 +# CHECK: r17 = vsubh(r31, r21) +0x11 0xdf 0xb5 0xf6 +# CHECK: r17 = vsubh(r31, r21):sat +0x11 0xdf 0xf5 0xf6 +# CHECK: r17 = vsubuh(r31, r21):sat + +# Zero extend 0x11 0xc0 0xd5 0x70 # CHECK: r17 = zxth(r21)