6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-09 13:33:17 +00:00
Code Issues Projects Releases Wiki Activity

fix PR8961 - a fast isel miscompilation where we'd insert a new instruction

Browse Source 
after sext's generated for addressing that got folded.  Previously we compiled
test5 into:

_test5:                                 ## @test5
## BB#0:
        movq    -8(%rsp), %rax          ## 8-byte Reload
        movq    (%rdi,%rax), %rdi
        addq    %rdx, %rdi
        movslq  %esi, %rax
        movq    %rax, -8(%rsp)          ## 8-byte Spill
        movq    %rdi, %rax
        ret

which is insane and wrong.  Now we produce:

_test5:                                 ## @test5
## BB#0:
	movslq	%esi, %rax
	movq	(%rdi,%rax), %rax
	addq	%rdx, %rax
	ret



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123414 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2011-01-14 00:01:01 +00:00
parent eea666f216
commit d754041493
2 changed files with 18 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/X86/X86FastISel.cpp
View File

@ -1933,7 +1933,7 @@ bool X86FastISel::TryToFoldLoad(MachineInstr *MI, unsigned OpNo,
XII.foldMemoryOperandImpl(*FuncInfo.MF, MI, OpNo, AddrOps, Size, Alignment);
if (Result == 0) return false;
MI->getParent()->insert(MI, Result);
FuncInfo.MBB->insert(FuncInfo.InsertPt, Result);
MI->eraseFromParent();
return true;
}

17
test/CodeGen/X86/fast-isel-gep.ll
View File

@ -70,3 +70,20 @@ entry:
; X64: test4:
; X64: 128(%r{{.*}},%r{{.*}},8)
}
; PR8961 - Make sure the sext for the GEP addressing comes before the load that
; is folded.
define i64 @test5(i8* %A, i32 %I, i64 %B) nounwind {
%v8 = getelementptr i8* %A, i32 %I
%v9 = bitcast i8* %v8 to i64*
%v10 = load i64* %v9
%v11 = add i64 %B, %v10
ret i64 %v11
; X64: test5:
; X64: movslq %esi, %rax
; X64-NEXT: movq (%rdi,%rax), %rax
; X64-NEXT: addq %rdx, %rax
; X64-NEXT: ret
}