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[ARM64] Fix a bug in shuffle vector lowering to generate corect vext ISD with swapped input vectors.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209495 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jiangning Liu 2014-05-23 02:54:50 +00:00
parent 0e93fa9d16
commit d7689b6ff6
2 changed files with 185 additions and 14 deletions
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27
lib/Target/ARM64/ARM64ISelLowering.cpp
View File

@ -4270,23 +4270,22 @@ static bool isEXTMask(ArrayRef<int> M, EVT VT, bool &ReverseEXT,
// The index of an EXT is the first element if it is not UNDEF. // The index of an EXT is the first element if it is not UNDEF.
// Watch out for the beginning UNDEFs. The EXT index should be the expected // Watch out for the beginning UNDEFs. The EXT index should be the expected
// value of the first element. // value of the first element. E.g.
// E.g. <-1, -1, 3, ...> is treated as <1, 2, 3, ...>. // <-1, -1, 3, ...> is treated as <1, 2, 3, ...>.
// <-1, -1, 0, 1, ...> is treated as <IDX, IDX+1, 0, 1, ...>. IDX is // <-1, -1, 0, 1, ...> is treated as <2*NumElts-2, 2*NumElts-1, 0, 1, ...>.
// equal to the ExpectedElt. // ExpectedElt is the last mask index plus 1.
Imm = (M[0] >= 0) ? static_cast<unsigned>(M[0]) : ExpectedElt.getZExtValue(); Imm = ExpectedElt.getZExtValue();
// If no beginning UNDEFs, do swap when M[0] >= NumElts. // There are two difference cases requiring to reverse input vectors.
if (M[0] >= 0 && Imm >= NumElts) { // For example, for vector <4 x i32> we have the following cases,
// Case 1: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, -1, 0>)
// Case 2: shufflevector(<4 x i32>,<4 x i32>,<-1, -1, 7, 0>)
// For both cases, we finally use mask <5, 6, 7, 0>, which requires
// to reverse two input vectors.
if (Imm < NumElts)
ReverseEXT = true; ReverseEXT = true;
else
Imm -= NumElts; Imm -= NumElts;
} else if (M[0] < 0) {
// Only do swap when beginning UNDEFs more than the first real element,
if (*FirstRealElt < FirstRealElt - M.begin())
ReverseEXT = true;
if (Imm >= NumElts)
Imm -= NumElts;
}
return true; return true;
} }

172
test/CodeGen/ARM64/vext_reverse.ll Normal file
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@ -0,0 +1,172 @@
; RUN: llc -mtriple=arm64-linux-gnuabi < %s | FileCheck %s
; The following tests is to check the correctness of reversing input operand
; of vext by enumerating all cases of using two undefs in shuffle masks.
define <4 x i16> @vext_6701_0(<4 x i16> %a1, <4 x i16> %a2) {
entry:
; CHECK-LABEL: vext_6701_0:
; CHECK: ext v0.8b, v1.8b, v0.8b, #4
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 7, i32 0, i32 1>
ret <4 x i16> %x
}
define <4 x i16> @vext_6701_12(<4 x i16> %a1, <4 x i16> %a2) {
entry:
; CHECK-LABEL: vext_6701_12:
; CHECK: ext v0.8b, v0.8b, v0.8b, #4
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 undef, i32 0, i32 1>
ret <4 x i16> %x
}
define <4 x i16> @vext_6701_13(<4 x i16> %a1, <4 x i16> %a2) {
entry:
; CHECK-LABEL: vext_6701_13:
; CHECK: ext v0.8b, v1.8b, v0.8b, #4
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 7, i32 undef, i32 1>
ret <4 x i16> %x
}
define <4 x i16> @vext_6701_14(<4 x i16> %a1, <4 x i16> %a2) {
entry:
; CHECK-LABEL: vext_6701_14:
; CHECK: ext v0.8b, v1.8b, v0.8b, #4
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 7, i32 0, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_6701_23(<4 x i16> %a1, <4 x i16> %a2) {
entry:
; CHECK-LABEL: vext_6701_23:
; CHECK: ext v0.8b, v1.8b, v0.8b, #4
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 undef, i32 undef, i32 1>
ret <4 x i16> %x
}
define <4 x i16> @vext_6701_24(<4 x i16> %a1, <4 x i16> %a2) {
entry:
; CHECK-LABEL: vext_6701_24:
; CHECK: ext v0.8b, v1.8b, v0.8b, #4
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 undef, i32 0, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_6701_34(<4 x i16> %a1, <4 x i16> %a2) {
entry:
; CHECK-LABEL: vext_6701_34:
; CHECK: ext v0.8b, v1.8b, v0.8b, #4
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 6, i32 7, i32 undef, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_5670_0(<4 x i16> %a1, <4 x i16> %a2) {
entry:
; CHECK-LABEL: vext_5670_0:
; CHECK: ext v0.8b, v1.8b, v0.8b, #2
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 6, i32 7, i32 0>
ret <4 x i16> %x
}
define <4 x i16> @vext_5670_12(<4 x i16> %a1, <4 x i16> %a2) {
entry:
; CHECK-LABEL: vext_5670_12:
; CHECK: ext v0.8b, v1.8b, v0.8b, #2
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 undef, i32 7, i32 0>
ret <4 x i16> %x
}
define <4 x i16> @vext_5670_13(<4 x i16> %a1, <4 x i16> %a2) {
entry:
; CHECK-LABEL: vext_5670_13:
; CHECK: ext v0.8b, v1.8b, v0.8b, #2
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 6, i32 undef, i32 0>
ret <4 x i16> %x
}
define <4 x i16> @vext_5670_14(<4 x i16> %a1, <4 x i16> %a2) {
entry:
; CHECK-LABEL: vext_5670_14:
; CHECK: ext v0.8b, v1.8b, v0.8b, #2
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 6, i32 7, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_5670_23(<4 x i16> %a1, <4 x i16> %a2) {
entry:
; CHECK-LABEL: vext_5670_23:
; CHECK: ext v0.8b, v1.8b, v0.8b, #2
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 undef, i32 undef, i32 0>
ret <4 x i16> %x
}
define <4 x i16> @vext_5670_24(<4 x i16> %a1, <4 x i16> %a2) {
entry:
; CHECK-LABEL: vext_5670_24:
; CHECK: rev32 v0.4h, v1.4h
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 undef, i32 7, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_5670_34(<4 x i16> %a1, <4 x i16> %a2) {
entry:
; CHECK-LABEL: vext_5670_34:
; CHECK: ext v0.8b, v1.8b, v0.8b, #2
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 5, i32 6, i32 undef, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_7012_0(<4 x i16> %a1, <4 x i16> %a2) {
entry:
; CHECK-LABEL: vext_7012_0:
; CHECK: ext v0.8b, v1.8b, v0.8b, #6
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 0, i32 1, i32 2>
ret <4 x i16> %x
}
define <4 x i16> @vext_7012_12(<4 x i16> %a1, <4 x i16> %a2) {
entry:
; CHECK-LABEL: vext_7012_12:
; CHECK: ext v0.8b, v0.8b, v0.8b, #6
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 undef, i32 1, i32 2>
ret <4 x i16> %x
}
define <4 x i16> @vext_7012_13(<4 x i16> %a1, <4 x i16> %a2) {
entry:
; CHECK-LABEL: vext_7012_13:
; CHECK: rev32 v0.4h, v0.4h
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 0, i32 undef, i32 2>
ret <4 x i16> %x
}
define <4 x i16> @vext_7012_14(<4 x i16> %a1, <4 x i16> %a2) {
entry:
; CHECK-LABEL: vext_7012_14:
; CHECK: ext v0.8b, v0.8b, v0.8b, #6
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 undef, i32 0, i32 1, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_7012_23(<4 x i16> %a1, <4 x i16> %a2) {
entry:
; CHECK-LABEL: vext_7012_23:
; CHECK: ext v0.8b, v1.8b, v0.8b, #6
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 undef, i32 undef, i32 2>
ret <4 x i16> %x
}
define <4 x i16> @vext_7012_24(<4 x i16> %a1, <4 x i16> %a2) {
entry:
; CHECK-LABEL: vext_7012_24:
; CHECK: ext v0.8b, v1.8b, v0.8b, #6
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 undef, i32 1, i32 undef>
ret <4 x i16> %x
}
define <4 x i16> @vext_7012_34(<4 x i16> %a1, <4 x i16> %a2) {
entry:
; CHECK-LABEL: vext_7012_34:
; CHECK: ext v0.8b, v1.8b, v0.8b, #6
%x = shufflevector <4 x i16> %a1, <4 x i16> %a2, <4 x i32> <i32 7, i32 0, i32 undef, i32 undef>
ret <4 x i16> %x
}