diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td index a52e52694a7..030f2275bd9 100644 --- a/lib/Target/Mips/Mips.td +++ b/lib/Target/Mips/Mips.td @@ -125,7 +125,8 @@ def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion", def FeatureMips64r6 : SubtargetFeature<"mips64r6", "MipsArchVersion", "Mips64r6", "Mips64r6 ISA Support [experimental]", - [FeatureMips64r2, FeatureNaN2008]>; + [FeatureMips32r6, FeatureMips64r2, + FeatureNaN2008]>; def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true", "Mips16 mode">; diff --git a/lib/Target/Mips/Mips32r6InstrFormats.td b/lib/Target/Mips/Mips32r6InstrFormats.td new file mode 100644 index 00000000000..241cde2a825 --- /dev/null +++ b/lib/Target/Mips/Mips32r6InstrFormats.td @@ -0,0 +1,34 @@ +//=- Mips32r6InstrFormats.td - Mips32r6 Instruction Formats -*- tablegen -*-==// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file describes Mips32r6 instruction formats. +// +//===----------------------------------------------------------------------===// + +class MipsR6Inst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, + PredicateControl { + let DecoderNamespace = "Mips32r6_64r6"; + let EncodingPredicates = [HasStdEnc]; +} + +class SPECIAL_3R_FM mulop, bits<6> funct> : MipsR6Inst { + bits<5> rd; + bits<5> rs; + bits<5> rt; + + bits<32> Inst; + + let Inst{31-26} = 0b00000; + let Inst{25-21} = rs; + let Inst{20-16} = rt; + let Inst{15-11} = rd; + let Inst{10-6} = mulop; + let Inst{5-0} = funct; +} + diff --git a/lib/Target/Mips/Mips32r6InstrInfo.td b/lib/Target/Mips/Mips32r6InstrInfo.td index a1f78dd928e..57bde6fc539 100644 --- a/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/lib/Target/Mips/Mips32r6InstrInfo.td @@ -11,6 +11,8 @@ // //===----------------------------------------------------------------------===// +include "Mips32r6InstrFormats.td" + // Notes about removals/changes from MIPS32r6: // Unclear: ssnop // Reencoded: cache, pref @@ -52,6 +54,41 @@ // Removed: teqi, tgei, tgeiu, tlti, tltiu, tnei // Rencoded: [ls][wd]c2 +//===----------------------------------------------------------------------===// +// +// Instruction Encodings +// +//===----------------------------------------------------------------------===// + +class MUH_ENC : SPECIAL_3R_FM<0b00011, 0b011000>; +class MUHU_ENC : SPECIAL_3R_FM<0b00011, 0b011001>; +class MUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b011000>; +class MULU_ENC : SPECIAL_3R_FM<0b00010, 0b011001>; + +//===----------------------------------------------------------------------===// +// +// Instruction Descriptions +// +//===----------------------------------------------------------------------===// + +class MUL_R6_DESC_BASE { + dag OutOperandList = (outs GPROpnd:$rd); + dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt); + string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt"); + list Pattern = []; +} + +class MUH_DESC : MUL_R6_DESC_BASE<"muh", GPR32Opnd>; +class MUHU_DESC : MUL_R6_DESC_BASE<"muhu", GPR32Opnd>; +class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd>; +class MULU_DESC : MUL_R6_DESC_BASE<"mulu", GPR32Opnd>; + +//===----------------------------------------------------------------------===// +// +// Instruction Definitions +// +//===----------------------------------------------------------------------===// + def ADDIUPC; def ALIGN; // Known as as BALIGN in DSP ASE def ALUIPC; @@ -106,10 +143,10 @@ def MIN_D; def MOD; def MODU; def MSUBF; -def MUH; -def MUHU; -def MUL_R6; // Not to be confused with the old mul -def MULU; +def MUH : MUH_ENC, MUH_DESC, ISA_MIPS32R6; +def MUHU : MUHU_ENC, MUHU_DESC, ISA_MIPS32R6; +def MUL_R6 : MUL_R6_ENC, MUL_R6_DESC, ISA_MIPS32R6; +def MULU : MULU_ENC, MULU_DESC, ISA_MIPS32R6; def NAL; // BAL with rd=0 def RINT_D; def RINT_S; diff --git a/lib/Target/Mips/Mips64r6InstrInfo.td b/lib/Target/Mips/Mips64r6InstrInfo.td index bf15ef62eb8..9607f751aa0 100644 --- a/lib/Target/Mips/Mips64r6InstrInfo.td +++ b/lib/Target/Mips/Mips64r6InstrInfo.td @@ -19,6 +19,34 @@ // Removed: div, divu // Removed: ldl, ldr, ldle, ldre, sdl, sdr, sdle, sdre +//===----------------------------------------------------------------------===// +// +// Instruction Encodings +// +//===----------------------------------------------------------------------===// + +class DMUH_ENC : SPECIAL_3R_FM<0b00011, 0b111000>; +class DMUHU_ENC : SPECIAL_3R_FM<0b00011, 0b111001>; +class DMUL_R6_ENC : SPECIAL_3R_FM<0b00010, 0b111000>; +class DMULU_ENC : SPECIAL_3R_FM<0b00010, 0b111001>; + +//===----------------------------------------------------------------------===// +// +// Instruction Descriptions +// +//===----------------------------------------------------------------------===// + +class DMUH_DESC : MUL_R6_DESC_BASE<"dmuh", GPR64Opnd>; +class DMUHU_DESC : MUL_R6_DESC_BASE<"dmuhu", GPR64Opnd>; +class DMUL_R6_DESC : MUL_R6_DESC_BASE<"dmul", GPR64Opnd>; +class DMULU_DESC : MUL_R6_DESC_BASE<"dmulu", GPR64Opnd>; + +//===----------------------------------------------------------------------===// +// +// Instruction Definitions +// +//===----------------------------------------------------------------------===// + def DAHI; def DALIGN; def DATI; @@ -29,8 +57,8 @@ def DDIVU; // def DLSA; // See MSA def DMOD; def DMODU; -def DMUH; -def DMUHU; -def DMUL_R6; // Not to be confused with the old mul -def DMULU; +def DMUH: DMUH_ENC, DMUH_DESC, ISA_MIPS64R6; +def DMUHU: DMUHU_ENC, DMUHU_DESC, ISA_MIPS64R6; +def DMUL_R6: DMUL_R6_ENC, DMUL_R6_DESC, ISA_MIPS64R6; +def DMULU: DMULU_ENC, DMULU_DESC, ISA_MIPS64R6; def LDPC; diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td index 1ae43ecf428..f00833e1e49 100644 --- a/lib/Target/Mips/MipsInstrInfo.td +++ b/lib/Target/Mips/MipsInstrInfo.td @@ -162,6 +162,8 @@ def HasMips32 : Predicate<"Subtarget.hasMips32()">, AssemblerPredicate<"FeatureMips32">; def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">, AssemblerPredicate<"FeatureMips32r2">; +def HasMips32r6 : Predicate<"Subtarget.hasMips32r6()">, + AssemblerPredicate<"FeatureMips32r6">; def IsGP64bit : Predicate<"Subtarget.isGP64bit()">, AssemblerPredicate<"FeatureGP64Bit">; def IsGP32bit : Predicate<"!Subtarget.isGP64bit()">, @@ -174,6 +176,8 @@ def IsGP64 : Predicate<"Subtarget.isGP64()">, AssemblerPredicate<"FeatureGP64Bit">; def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">, AssemblerPredicate<"FeatureMips64r2">; +def HasMips64r6 : Predicate<"Subtarget.hasMips64r6()">, + AssemblerPredicate<"FeatureMips64r6">; def IsN64 : Predicate<"Subtarget.isABI_N64()">, AssemblerPredicate<"FeatureN64">; def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">, @@ -214,6 +218,8 @@ class ISA_MIPS32 { list InsnPredicates = [HasMips32]; } class ISA_MIPS32R2 { list InsnPredicates = [HasMips32r2]; } class ISA_MIPS64 { list InsnPredicates = [HasMips64]; } class ISA_MIPS64R2 { list InsnPredicates = [HasMips64r2]; } +class ISA_MIPS32R6 { list InsnPredicates = [HasMips32r6]; } +class ISA_MIPS64R6 { list InsnPredicates = [HasMips64r6]; } // The portions of MIPS-III that were also added to MIPS32 class INSN_MIPS3_32 { list InsnPredicates = [HasMips3_32]; } diff --git a/test/MC/Mips/mips32r6/valid.s b/test/MC/Mips/mips32r6/valid.s new file mode 100644 index 00000000000..ad4d322ff3c --- /dev/null +++ b/test/MC/Mips/mips32r6/valid.s @@ -0,0 +1,10 @@ +# Instructions that are valid +# +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 | FileCheck %s + + .set noat + # FIXME: Add the instructions carried forward from older ISA's +# mul $2,$3,$4 # CHECK-TODO: mul $2, $3, $4 # encoding: [0x00,0x64,0x10,0x98] + muh $2,$3,$4 # CHECK: muh $2, $3, $4 # encoding: [0x00,0x64,0x10,0xd8] + mulu $2,$3,$4 # CHECK: mulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x99] + muhu $2,$3,$4 # CHECK: muhu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xd9] diff --git a/test/MC/Mips/mips64r6/valid.s b/test/MC/Mips/mips64r6/valid.s new file mode 100644 index 00000000000..214a8ab53ce --- /dev/null +++ b/test/MC/Mips/mips64r6/valid.s @@ -0,0 +1,14 @@ +# Instructions that are valid +# +# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips64r6 | FileCheck %s + + .set noat + # FIXME: Add the instructions carried forward from older ISA's +# mul $2,$3,$4 # CHECK-TODO: mul $2, $3, $4 # encoding: [0x00,0x64,0x10,0x98] + muh $2,$3,$4 # CHECK: muh $2, $3, $4 # encoding: [0x00,0x64,0x10,0xd8] + mulu $2,$3,$4 # CHECK: mulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0x99] + muhu $2,$3,$4 # CHECK: muhu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xd9] + dmul $2,$3,$4 # CHECK: dmul $2, $3, $4 # encoding: [0x00,0x64,0x10,0xb8] + dmuh $2,$3,$4 # CHECK: dmuh $2, $3, $4 # encoding: [0x00,0x64,0x10,0xf8] + dmulu $2,$3,$4 # CHECK: dmulu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xb9] + dmuhu $2,$3,$4 # CHECK: dmuhu $2, $3, $4 # encoding: [0x00,0x64,0x10,0xf9]