6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-05 12:31:33 +00:00
Code Issues Projects Releases Wiki Activity

cleanup

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162820 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2012-08-29 01:58:52 +00:00
parent 68990df1f9
commit d79dedd458
1 changed files with 19 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

40
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -705,28 +705,26 @@ void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg))
Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4, Spacing = 2; Opc = ARM::VMOVD, BeginIdx = ARM::dsub_0, SubRegs = 4, Spacing = 2;
if (Opc) { if (!Opc)
const TargetRegisterInfo *TRI = &getRegisterInfo(); llvm_unreachable("Impossible reg-to-reg copy");
MachineInstrBuilder Mov;
for (unsigned i = 0; i != SubRegs; ++i) {
unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i*Spacing);
unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i*Spacing);
assert(Dst && Src && "Bad sub-register");
Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst)
.addReg(Src);
// VORR takes two source operands.
if (Opc == ARM::VORRq)
Mov.addReg(Src);
Mov = AddDefaultPred(Mov);
}
// Add implicit super-register defs and kills to the last instruction.
Mov->addRegisterDefined(DestReg, TRI);
if (KillSrc)
Mov->addRegisterKilled(SrcReg, TRI);
return;
}
llvm_unreachable("Impossible reg-to-reg copy"); const TargetRegisterInfo *TRI = &getRegisterInfo();
MachineInstrBuilder Mov;
for (unsigned i = 0; i != SubRegs; ++i) {
unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i*Spacing);
unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i*Spacing);
assert(Dst && Src && "Bad sub-register");
Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst)
.addReg(Src);
// VORR takes two source operands.
if (Opc == ARM::VORRq)
Mov.addReg(Src);
Mov = AddDefaultPred(Mov);
}
// Add implicit super-register defs and kills to the last instruction.
Mov->addRegisterDefined(DestReg, TRI);
if (KillSrc)
Mov->addRegisterKilled(SrcReg, TRI);
} }
static const static const