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Add {mix,max}{ss,sd}{rr,rm} AVX forms.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106264 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes 2010-06-18 01:12:56 +00:00
parent 8a7f7426ee
commit d7f9cc4de7
3 changed files with 90 additions and 22 deletions
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47
lib/Target/X86/X86InstrSSE.td
View File

@ -857,30 +857,31 @@ let Constraints = "$src1 = $dst" in {
multiclass sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
SDNode OpNode, bit Commutable = 0> {
// Scalar operation, reg+reg.
def SSrr : SSI<opc, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src1, FR32:$src2),
!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
[(set FR32:$dst, (OpNode FR32:$src1, FR32:$src2))]> {
let isCommutable = Commutable;
let Constraints = "", isAsmParserOnly = 1, hasVEX_4VPrefix = 1 in {
// Scalar operation, reg+reg.
let Prefix = 12 /* XS */ in
defm V#NAME#SS : sse12_fp_scalar<opc,
!strconcat(OpcodeStr, "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
OpNode, FR32, f32mem>;
let Prefix = 11 /* XD */ in
defm V#NAME#SD : sse12_fp_scalar<opc,
!strconcat(OpcodeStr, "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
OpNode, FR64, f64mem>;
}
def SDrr : SDI<opc, MRMSrcReg, (outs FR64:$dst), (ins FR64:$src1, FR64:$src2),
!strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
[(set FR64:$dst, (OpNode FR64:$src1, FR64:$src2))]> {
let isCommutable = Commutable;
let Constraints = "$src1 = $dst" in {
// Scalar operation, reg+reg.
let Prefix = 12 /* XS */ in
defm SS : sse12_fp_scalar<opc,
!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
OpNode, FR32, f32mem>;
let Prefix = 11 /* XD */ in
defm SD : sse12_fp_scalar<opc,
!strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
OpNode, FR64, f64mem>;
}
// Scalar operation, reg+mem.
def SSrm : SSI<opc, MRMSrcMem, (outs FR32:$dst),
(ins FR32:$src1, f32mem:$src2),
!strconcat(OpcodeStr, "ss\t{$src2, $dst|$dst, $src2}"),
[(set FR32:$dst, (OpNode FR32:$src1, (load addr:$src2)))]>;
def SDrm : SDI<opc, MRMSrcMem, (outs FR64:$dst),
(ins FR64:$src1, f64mem:$src2),
!strconcat(OpcodeStr, "sd\t{$src2, $dst|$dst, $src2}"),
[(set FR64:$dst, (OpNode FR64:$src1, (load addr:$src2)))]>;
// Vector operation, reg+reg.
def PSrr : PSI<opc, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2),
@ -985,8 +986,10 @@ multiclass sse12_fp_binop_rm<bits<8> opc, string OpcodeStr,
}
}
defm MAX : sse12_fp_binop_rm<0x5F, "max", X86fmax>;
defm MIN : sse12_fp_binop_rm<0x5D, "min", X86fmin>;
let isCommutable = 0 in {
defm MAX : sse12_fp_binop_rm<0x5F, "max", X86fmax>;
defm MIN : sse12_fp_binop_rm<0x5D, "min", X86fmin>;
}
//===----------------------------------------------------------------------===//
// SSE packed FP Instructions

32
test/MC/AsmParser/X86/x86_32-encoding.s
View File

@ -10180,3 +10180,35 @@ pshufb CPI1_0(%rip), %xmm1
// CHECK: vdivpd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
// CHECK: encoding: [0xc5,0xe9,0x5e,0xac,0xcb,0xef,0xbe,0xad,0xde]
vdivpd 3735928559(%ebx,%ecx,8), %xmm2, %xmm5
// CHECK: vmaxss %xmm2, %xmm4, %xmm6
// CHECK: encoding: [0xc5,0xda,0x5f,0xf2]
vmaxss %xmm2, %xmm4, %xmm6
// CHECK: vmaxsd %xmm2, %xmm4, %xmm6
// CHECK: encoding: [0xc5,0xdb,0x5f,0xf2]
vmaxsd %xmm2, %xmm4, %xmm6
// CHECK: vminss %xmm2, %xmm4, %xmm6
// CHECK: encoding: [0xc5,0xda,0x5d,0xf2]
vminss %xmm2, %xmm4, %xmm6
// CHECK: vminsd %xmm2, %xmm4, %xmm6
// CHECK: encoding: [0xc5,0xdb,0x5d,0xf2]
vminsd %xmm2, %xmm4, %xmm6
// CHECK: vmaxss -4(%ebx,%ecx,8), %xmm2, %xmm5
// CHECK: encoding: [0xc5,0xea,0x5f,0x6c,0xcb,0xfc]
vmaxss -4(%ebx,%ecx,8), %xmm2, %xmm5
// CHECK: vmaxsd -4(%ebx,%ecx,8), %xmm2, %xmm5
// CHECK: encoding: [0xc5,0xeb,0x5f,0x6c,0xcb,0xfc]
vmaxsd -4(%ebx,%ecx,8), %xmm2, %xmm5
// CHECK: vminss -4(%ebx,%ecx,8), %xmm2, %xmm5
// CHECK: encoding: [0xc5,0xea,0x5d,0x6c,0xcb,0xfc]
vminss -4(%ebx,%ecx,8), %xmm2, %xmm5
// CHECK: vminsd -4(%ebx,%ecx,8), %xmm2, %xmm5
// CHECK: encoding: [0xc5,0xeb,0x5d,0x6c,0xcb,0xfc]
vminsd -4(%ebx,%ecx,8), %xmm2, %xmm5

33
test/MC/AsmParser/X86/x86_64-encoding.s
View File

@ -231,3 +231,36 @@ vmulpd -4(%rcx,%rbx,8), %xmm10, %xmm11
// CHECK: vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11
// CHECK: encoding: [0xc5,0x29,0x5e,0x5c,0xd9,0xfc]
vdivpd -4(%rcx,%rbx,8), %xmm10, %xmm11
// CHECK: vmaxss %xmm10, %xmm14, %xmm12
// CHECK: encoding: [0xc4,0x41,0x0a,0x5f,0xe2]
vmaxss %xmm10, %xmm14, %xmm12
// CHECK: vmaxsd %xmm10, %xmm14, %xmm12
// CHECK: encoding: [0xc4,0x41,0x0b,0x5f,0xe2]
vmaxsd %xmm10, %xmm14, %xmm12
// CHECK: vminss %xmm10, %xmm14, %xmm12
// CHECK: encoding: [0xc4,0x41,0x0a,0x5d,0xe2]
vminss %xmm10, %xmm14, %xmm12
// CHECK: vminsd %xmm10, %xmm14, %xmm12
// CHECK: encoding: [0xc4,0x41,0x0b,0x5d,0xe2]
vminsd %xmm10, %xmm14, %xmm12
// CHECK: vmaxss -4(%rbx,%rcx,8), %xmm12, %xmm10
// CHECK: encoding: [0xc5,0x1a,0x5f,0x54,0xcb,0xfc]
vmaxss -4(%rbx,%rcx,8), %xmm12, %xmm10
// CHECK: vmaxsd -4(%rbx,%rcx,8), %xmm12, %xmm10
// CHECK: encoding: [0xc5,0x1b,0x5f,0x54,0xcb,0xfc]
vmaxsd -4(%rbx,%rcx,8), %xmm12, %xmm10
// CHECK: vminss -4(%rbx,%rcx,8), %xmm12, %xmm10
// CHECK: encoding: [0xc5,0x1a,0x5d,0x54,0xcb,0xfc]
vminss -4(%rbx,%rcx,8), %xmm12, %xmm10
// CHECK: vminsd -4(%rbx,%rcx,8), %xmm12, %xmm10
// CHECK: encoding: [0xc5,0x1b,0x5d,0x54,0xcb,0xfc]
vminsd -4(%rbx,%rcx,8), %xmm12, %xmm10