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PTX: Always use registers for return values, but use .param space for device

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parameters if SM >= 2.0

- Update test cases to be more robust against register allocation changes
- Bump up the number of registers to 128 per type
- Include Python script to re-generate register file with any number of
  registers

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133736 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Justin Holewinski
2011-06-23 18:10:13 +00:00
parent 6b1131e5ff
commit d8149c1bef
26 changed files with 1043 additions and 403 deletions
Download Patch File Download Diff File Expand all files Collapse all files

92
test/CodeGen/PTX/setp.ll
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@@ -1,8 +1,8 @@
; RUN: llc < %s -march=ptx32 | FileCheck %s
define ptx_device i32 @test_setp_eq_u32_rr(i32 %x, i32 %y) {
; CHECK: setp.eq.u32 p0, r1, r2;
; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
; CHECK: setp.eq.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
; CHECK-NEXT: ret;
%p = icmp eq i32 %x, %y
%z = zext i1 %p to i32
@@ -10,8 +10,8 @@ define ptx_device i32 @test_setp_eq_u32_rr(i32 %x, i32 %y) {
}
define ptx_device i32 @test_setp_ne_u32_rr(i32 %x, i32 %y) {
; CHECK: setp.ne.u32 p0, r1, r2;
; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
; CHECK: setp.ne.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
; CHECK-NEXT: ret;
%p = icmp ne i32 %x, %y
%z = zext i1 %p to i32
@@ -19,8 +19,8 @@ define ptx_device i32 @test_setp_ne_u32_rr(i32 %x, i32 %y) {
}
define ptx_device i32 @test_setp_lt_u32_rr(i32 %x, i32 %y) {
; CHECK: setp.lt.u32 p0, r1, r2;
; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
; CHECK: setp.lt.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
; CHECK-NEXT: ret;
%p = icmp ult i32 %x, %y
%z = zext i1 %p to i32
@@ -28,8 +28,8 @@ define ptx_device i32 @test_setp_lt_u32_rr(i32 %x, i32 %y) {
}
define ptx_device i32 @test_setp_le_u32_rr(i32 %x, i32 %y) {
; CHECK: setp.le.u32 p0, r1, r2;
; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
; CHECK: setp.le.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
; CHECK-NEXT: ret;
%p = icmp ule i32 %x, %y
%z = zext i1 %p to i32
@@ -37,8 +37,8 @@ define ptx_device i32 @test_setp_le_u32_rr(i32 %x, i32 %y) {
}
define ptx_device i32 @test_setp_gt_u32_rr(i32 %x, i32 %y) {
; CHECK: setp.gt.u32 p0, r1, r2;
; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
; CHECK: setp.gt.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
; CHECK-NEXT: ret;
%p = icmp ugt i32 %x, %y
%z = zext i1 %p to i32
@@ -46,8 +46,8 @@ define ptx_device i32 @test_setp_gt_u32_rr(i32 %x, i32 %y) {
}
define ptx_device i32 @test_setp_ge_u32_rr(i32 %x, i32 %y) {
; CHECK: setp.ge.u32 p0, r1, r2;
; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
; CHECK: setp.ge.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
; CHECK-NEXT: ret;
%p = icmp uge i32 %x, %y
%z = zext i1 %p to i32
@@ -55,8 +55,8 @@ define ptx_device i32 @test_setp_ge_u32_rr(i32 %x, i32 %y) {
}
define ptx_device i32 @test_setp_lt_s32_rr(i32 %x, i32 %y) {
; CHECK: setp.lt.s32 p0, r1, r2;
; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
; CHECK: setp.lt.s32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
; CHECK-NEXT: ret;
%p = icmp slt i32 %x, %y
%z = zext i1 %p to i32
@@ -64,8 +64,8 @@ define ptx_device i32 @test_setp_lt_s32_rr(i32 %x, i32 %y) {
}
define ptx_device i32 @test_setp_le_s32_rr(i32 %x, i32 %y) {
; CHECK: setp.le.s32 p0, r1, r2;
; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
; CHECK: setp.le.s32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
; CHECK-NEXT: ret;
%p = icmp sle i32 %x, %y
%z = zext i1 %p to i32
@@ -73,8 +73,8 @@ define ptx_device i32 @test_setp_le_s32_rr(i32 %x, i32 %y) {
}
define ptx_device i32 @test_setp_gt_s32_rr(i32 %x, i32 %y) {
; CHECK: setp.gt.s32 p0, r1, r2;
; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
; CHECK: setp.gt.s32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
; CHECK-NEXT: ret;
%p = icmp sgt i32 %x, %y
%z = zext i1 %p to i32
@@ -82,8 +82,8 @@ define ptx_device i32 @test_setp_gt_s32_rr(i32 %x, i32 %y) {
}
define ptx_device i32 @test_setp_ge_s32_rr(i32 %x, i32 %y) {
; CHECK: setp.ge.s32 p0, r1, r2;
; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
; CHECK: setp.ge.s32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
; CHECK-NEXT: ret;
%p = icmp sge i32 %x, %y
%z = zext i1 %p to i32
@@ -91,8 +91,8 @@ define ptx_device i32 @test_setp_ge_s32_rr(i32 %x, i32 %y) {
}
define ptx_device i32 @test_setp_eq_u32_ri(i32 %x) {
; CHECK: setp.eq.u32 p0, r1, 1;
; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
; CHECK: setp.eq.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, 1;
; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
; CHECK-NEXT: ret;
%p = icmp eq i32 %x, 1
%z = zext i1 %p to i32
@@ -100,8 +100,8 @@ define ptx_device i32 @test_setp_eq_u32_ri(i32 %x) {
}
define ptx_device i32 @test_setp_ne_u32_ri(i32 %x) {
; CHECK: setp.ne.u32 p0, r1, 1;
; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
; CHECK: setp.ne.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, 1;
; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
; CHECK-NEXT: ret;
%p = icmp ne i32 %x, 1
%z = zext i1 %p to i32
@@ -109,8 +109,8 @@ define ptx_device i32 @test_setp_ne_u32_ri(i32 %x) {
}
define ptx_device i32 @test_setp_lt_u32_ri(i32 %x) {
; CHECK: setp.eq.u32 p0, r1, 0;
; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
; CHECK: setp.eq.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0;
; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
; CHECK-NEXT: ret;
%p = icmp ult i32 %x, 1
%z = zext i1 %p to i32
@@ -118,8 +118,8 @@ define ptx_device i32 @test_setp_lt_u32_ri(i32 %x) {
}
define ptx_device i32 @test_setp_le_u32_ri(i32 %x) {
; CHECK: setp.lt.u32 p0, r1, 2;
; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
; CHECK: setp.lt.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, 2;
; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
; CHECK-NEXT: ret;
%p = icmp ule i32 %x, 1
%z = zext i1 %p to i32
@@ -127,8 +127,8 @@ define ptx_device i32 @test_setp_le_u32_ri(i32 %x) {
}
define ptx_device i32 @test_setp_gt_u32_ri(i32 %x) {
; CHECK: setp.gt.u32 p0, r1, 1;
; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
; CHECK: setp.gt.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, 1;
; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
; CHECK-NEXT: ret;
%p = icmp ugt i32 %x, 1
%z = zext i1 %p to i32
@@ -136,8 +136,8 @@ define ptx_device i32 @test_setp_gt_u32_ri(i32 %x) {
}
define ptx_device i32 @test_setp_ge_u32_ri(i32 %x) {
; CHECK: setp.ne.u32 p0, r1, 0;
; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
; CHECK: setp.ne.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0;
; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
; CHECK-NEXT: ret;
%p = icmp uge i32 %x, 1
%z = zext i1 %p to i32
@@ -145,8 +145,8 @@ define ptx_device i32 @test_setp_ge_u32_ri(i32 %x) {
}
define ptx_device i32 @test_setp_lt_s32_ri(i32 %x) {
; CHECK: setp.lt.s32 p0, r1, 1;
; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
; CHECK: setp.lt.s32 p[[P0:[0-9]+]], r{{[0-9]+}}, 1;
; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
; CHECK-NEXT: ret;
%p = icmp slt i32 %x, 1
%z = zext i1 %p to i32
@@ -154,8 +154,8 @@ define ptx_device i32 @test_setp_lt_s32_ri(i32 %x) {
}
define ptx_device i32 @test_setp_le_s32_ri(i32 %x) {
; CHECK: setp.lt.s32 p0, r1, 2;
; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
; CHECK: setp.lt.s32 p[[P0:[0-9]+]], r{{[0-9]+}}, 2;
; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
; CHECK-NEXT: ret;
%p = icmp sle i32 %x, 1
%z = zext i1 %p to i32
@@ -163,8 +163,8 @@ define ptx_device i32 @test_setp_le_s32_ri(i32 %x) {
}
define ptx_device i32 @test_setp_gt_s32_ri(i32 %x) {
; CHECK: setp.gt.s32 p0, r1, 1;
; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
; CHECK: setp.gt.s32 p[[P0:[0-9]+]], r{{[0-9]+}}, 1;
; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
; CHECK-NEXT: ret;
%p = icmp sgt i32 %x, 1
%z = zext i1 %p to i32
@@ -172,8 +172,8 @@ define ptx_device i32 @test_setp_gt_s32_ri(i32 %x) {
}
define ptx_device i32 @test_setp_ge_s32_ri(i32 %x) {
; CHECK: setp.gt.s32 p0, r1, 0;
; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
; CHECK: setp.gt.s32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0;
; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
; CHECK-NEXT: ret;
%p = icmp sge i32 %x, 1
%z = zext i1 %p to i32
@@ -181,9 +181,9 @@ define ptx_device i32 @test_setp_ge_s32_ri(i32 %x) {
}
define ptx_device i32 @test_setp_4_op_format_1(i32 %x, i32 %y, i32 %u, i32 %v) {
; CHECK: setp.gt.u32 p0, r3, r4;
; CHECK-NEXT: setp.eq.and.u32 p0, r1, r2, p0;
; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
; CHECK: setp.gt.u32 p[[P0:[0-9]+]], r{{[0-9]+}}, r{{[0-9]+}};
; CHECK-NEXT: setp.eq.and.u32 p[[P0]], r{{[0-9]+}}, r{{[0-9]+}}, p[[P0]];
; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
; CHECK-NEXT: ret;
%c = icmp eq i32 %x, %y
%d = icmp ugt i32 %u, %v
@@ -193,9 +193,9 @@ define ptx_device i32 @test_setp_4_op_format_1(i32 %x, i32 %y, i32 %u, i32 %v) {
}
define ptx_device i32 @test_setp_4_op_format_2(i32 %x, i32 %y, i32 %w) {
; CHECK: setp.gt.b32 p0, r3, 0;
; CHECK-NEXT: setp.eq.and.u32 p0, r1, r2, !p0;
; CHECK-NEXT: selp.u32 r0, 1, 0, p0;
; CHECK: setp.gt.b32 p[[P0:[0-9]+]], r{{[0-9]+}}, 0;
; CHECK-NEXT: setp.eq.and.u32 p[[P0]], r{{[0-9]+}}, r{{[0-9]+}}, !p[[P0]];
; CHECK-NEXT: selp.u32 r{{[0-9]+}}, 1, 0, p[[P0]];
; CHECK-NEXT: ret;
%c = trunc i32 %w to i1
%d = icmp eq i32 %x, %y