6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-06-13 04:38:24 +00:00
Code Issues Projects Releases Wiki Activity

Don't enable the post-RA scheduler on x86 except at -O3. In its

Browse Source 
current form, it is too expensive in compile time.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90781 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
2009-12-07 19:04:31 +00:00
parent 9a8641201b
commit d84ea47b89
9 changed files with 9 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/X86/X86Subtarget.cpp
View File

@ -367,5 +367,5 @@ bool X86Subtarget::enablePostRAScheduler(
RegClassVector& CriticalPathRCs) const { RegClassVector& CriticalPathRCs) const {
Mode = TargetSubtarget::ANTIDEP_CRITICAL; Mode = TargetSubtarget::ANTIDEP_CRITICAL;
CriticalPathRCs.clear(); CriticalPathRCs.clear();
return OptLevel >= CodeGenOpt::Default; return OptLevel >= CodeGenOpt::Aggressive;
} }

2
test/CodeGen/X86/2007-01-08-InstrSched.ll
View File

@ -1,5 +1,5 @@
; PR1075 ; PR1075
; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s ; RUN: llc < %s -mtriple=x86_64-apple-darwin -O3 | FileCheck %s
define float @foo(float %x) nounwind { define float @foo(float %x) nounwind {
%tmp1 = fmul float %x, 3.000000e+00 %tmp1 = fmul float %x, 3.000000e+00

2
test/CodeGen/X86/2009-09-19-SchedCustomLoweringBug.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=i386-apple-darwin10 | FileCheck %s ; RUN: llc < %s -mtriple=i386-apple-darwin10 -post-RA-scheduler=true | FileCheck %s
; PR4958 ; PR4958

2
test/CodeGen/X86/sink-hoist.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86-64 -asm-verbose=false -mtriple=x86_64-unknown-linux-gnu | FileCheck %s ; RUN: llc < %s -march=x86-64 -asm-verbose=false -mtriple=x86_64-unknown-linux-gnu -post-RA-scheduler=true | FileCheck %s
; Currently, floating-point selects are lowered to CFG triangles. ; Currently, floating-point selects are lowered to CFG triangles.
; This means that one side of the select is always unconditionally ; This means that one side of the select is always unconditionally

2
test/CodeGen/X86/sse2.ll
View File

@ -1,5 +1,5 @@
; Tests for SSE2 and below, without SSE3+. ; Tests for SSE2 and below, without SSE3+.
; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=pentium4 | FileCheck %s ; RUN: llc < %s -mtriple=i386-apple-darwin10 -mcpu=pentium4 -O3 | FileCheck %s
define void @t1(<2 x double>* %r, <2 x double>* %A, double %B) nounwind { define void @t1(<2 x double>* %r, <2 x double>* %A, double %B) nounwind {
%tmp3 = load <2 x double>* %A, align 16 %tmp3 = load <2 x double>* %A, align 16

2
test/CodeGen/X86/sse3.ll
View File

@ -1,6 +1,6 @@
; These are tests for SSE3 codegen. Yonah has SSE3 and earlier but not SSSE3+. ; These are tests for SSE3 codegen. Yonah has SSE3 and earlier but not SSSE3+.
; RUN: llc < %s -march=x86-64 -mcpu=yonah -mtriple=i686-apple-darwin9\ ; RUN: llc < %s -march=x86-64 -mcpu=yonah -mtriple=i686-apple-darwin9 -O3 \
; RUN: | FileCheck %s --check-prefix=X64 ; RUN: | FileCheck %s --check-prefix=X64
; Test for v8xi16 lowering where we extract the first element of the vector and ; Test for v8xi16 lowering where we extract the first element of the vector and

2
test/CodeGen/X86/tail-opts.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -asm-verbose=false | FileCheck %s ; RUN: llc < %s -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -asm-verbose=false -post-RA-scheduler=true | FileCheck %s
declare void @bar(i32) declare void @bar(i32)
declare void @car(i32) declare void @car(i32)

2
test/CodeGen/X86/tailcallstack64.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -tailcallopt -march=x86-64 | FileCheck %s ; RUN: llc < %s -tailcallopt -march=x86-64 -post-RA-scheduler=true | FileCheck %s
; Check that lowered arguments on the stack do not overwrite each other. ; Check that lowered arguments on the stack do not overwrite each other.
; Add %in1 %p1 to a different temporary register (%eax). ; Add %in1 %p1 to a different temporary register (%eax).

2
test/CodeGen/X86/widen_arith-3.ll
View File

@ -1,4 +1,4 @@
; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx | FileCheck %s ; RUN: llc < %s -march=x86 -mattr=+sse42 -disable-mmx -post-RA-scheduler=true | FileCheck %s
; CHECK: paddw ; CHECK: paddw
; CHECK: pextrw ; CHECK: pextrw
; CHECK: movd ; CHECK: movd