mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-10 04:33:40 +00:00
[FastISel][AArch64] Update function and variable names to follow the coding standard. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217845 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka
parent
1bdc6c4519
commit
d8629f313e
@ -115,37 +115,37 @@ private:
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// Selection routines.
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bool selectAddSub(const Instruction *I);
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bool selectLogicalOp(const Instruction *I);
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bool SelectLoad(const Instruction *I);
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bool SelectStore(const Instruction *I);
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bool SelectBranch(const Instruction *I);
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bool SelectIndirectBr(const Instruction *I);
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bool SelectCmp(const Instruction *I);
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bool SelectSelect(const Instruction *I);
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bool SelectFPExt(const Instruction *I);
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bool SelectFPTrunc(const Instruction *I);
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bool SelectFPToInt(const Instruction *I, bool Signed);
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bool SelectIntToFP(const Instruction *I, bool Signed);
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bool SelectRem(const Instruction *I, unsigned ISDOpcode);
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bool SelectRet(const Instruction *I);
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bool SelectTrunc(const Instruction *I);
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bool SelectIntExt(const Instruction *I);
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bool SelectMul(const Instruction *I);
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bool SelectShift(const Instruction *I);
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bool SelectBitCast(const Instruction *I);
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bool selectLoad(const Instruction *I);
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bool selectStore(const Instruction *I);
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bool selectBranch(const Instruction *I);
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bool selectIndirectBr(const Instruction *I);
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bool selectCmp(const Instruction *I);
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bool selectSelect(const Instruction *I);
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bool selectFPExt(const Instruction *I);
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bool selectFPTrunc(const Instruction *I);
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bool selectFPToInt(const Instruction *I, bool Signed);
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bool selectIntToFP(const Instruction *I, bool Signed);
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bool selectRem(const Instruction *I, unsigned ISDOpcode);
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bool selectRet(const Instruction *I);
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bool selectTrunc(const Instruction *I);
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bool selectIntExt(const Instruction *I);
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bool selectMul(const Instruction *I);
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bool selectShift(const Instruction *I);
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bool selectBitCast(const Instruction *I);
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bool selectFRem(const Instruction *I);
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// Utility helper routines.
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bool isTypeLegal(Type *Ty, MVT &VT);
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bool isTypeSupported(Type *Ty, MVT &VT, bool IsVectorAllowed = false);
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bool isValueAvailable(const Value *V) const;
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bool ComputeAddress(const Value *Obj, Address &Addr, Type *Ty = nullptr);
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bool ComputeCallAddress(const Value *V, Address &Addr);
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bool SimplifyAddress(Address &Addr, MVT VT);
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void AddLoadStoreOperands(Address &Addr, const MachineInstrBuilder &MIB,
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bool computeAddress(const Value *Obj, Address &Addr, Type *Ty = nullptr);
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bool computeCallAddress(const Value *V, Address &Addr);
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bool simplifyAddress(Address &Addr, MVT VT);
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void addLoadStoreOperands(Address &Addr, const MachineInstrBuilder &MIB,
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unsigned Flags, unsigned ScaleFactor,
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MachineMemOperand *MMO);
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bool IsMemCpySmall(uint64_t Len, unsigned Alignment);
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bool TryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
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bool isMemCpySmall(uint64_t Len, unsigned Alignment);
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bool tryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len,
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unsigned Alignment);
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bool foldXALUIntrinsic(AArch64CC::CondCode &CC, const Instruction *I,
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const Value *Cond);
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@ -176,12 +176,12 @@ private:
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bool emitICmp(MVT RetVT, const Value *LHS, const Value *RHS, bool IsZExt);
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bool emitICmp_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
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bool emitFCmp(MVT RetVT, const Value *LHS, const Value *RHS);
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bool EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
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bool emitLoad(MVT VT, unsigned &ResultReg, Address Addr,
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MachineMemOperand *MMO = nullptr);
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bool EmitStore(MVT VT, unsigned SrcReg, Address Addr,
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bool emitStore(MVT VT, unsigned SrcReg, Address Addr,
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MachineMemOperand *MMO = nullptr);
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unsigned EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
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unsigned Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
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unsigned emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt);
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unsigned emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt);
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unsigned emitAdd(MVT RetVT, const Value *LHS, const Value *RHS,
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bool SetFlags = false, bool WantResult = true,
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bool IsZExt = false);
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@ -202,11 +202,11 @@ private:
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bool LHSIsKill, unsigned RHSReg, bool RHSIsKill,
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uint64_t ShiftImm);
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unsigned emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill, uint64_t Imm);
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unsigned Emit_MUL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
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unsigned emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
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unsigned Op1, bool Op1IsKill);
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unsigned Emit_SMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
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unsigned emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
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unsigned Op1, bool Op1IsKill);
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unsigned Emit_UMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
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unsigned emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
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unsigned Op1, bool Op1IsKill);
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unsigned emitLSL_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
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unsigned Op1Reg, bool Op1IsKill);
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@ -221,16 +221,16 @@ private:
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unsigned emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0Reg, bool Op0IsKill,
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uint64_t Imm, bool IsZExt = false);
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unsigned AArch64MaterializeInt(const ConstantInt *CI, MVT VT);
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unsigned AArch64MaterializeFP(const ConstantFP *CFP, MVT VT);
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unsigned AArch64MaterializeGV(const GlobalValue *GV);
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unsigned materializeInt(const ConstantInt *CI, MVT VT);
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unsigned materializeFP(const ConstantFP *CFP, MVT VT);
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unsigned materializeGV(const GlobalValue *GV);
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// Call handling routines.
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private:
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CCAssignFn *CCAssignFnForCall(CallingConv::ID CC) const;
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bool ProcessCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
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bool processCallArgs(CallLoweringInfo &CLI, SmallVectorImpl<MVT> &ArgVTs,
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unsigned &NumBytes);
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bool FinishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
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bool finishCall(CallLoweringInfo &CLI, MVT RetVT, unsigned NumBytes);
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public:
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// Backend specific FastISel code.
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@ -284,7 +284,7 @@ unsigned AArch64FastISel::fastMaterializeAlloca(const AllocaInst *AI) {
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return 0;
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}
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unsigned AArch64FastISel::AArch64MaterializeInt(const ConstantInt *CI, MVT VT) {
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unsigned AArch64FastISel::materializeInt(const ConstantInt *CI, MVT VT) {
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if (VT > MVT::i64)
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return 0;
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@ -301,7 +301,7 @@ unsigned AArch64FastISel::AArch64MaterializeInt(const ConstantInt *CI, MVT VT) {
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return ResultReg;
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}
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unsigned AArch64FastISel::AArch64MaterializeFP(const ConstantFP *CFP, MVT VT) {
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unsigned AArch64FastISel::materializeFP(const ConstantFP *CFP, MVT VT) {
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// Positive zero (+0.0) has to be materialized with a fmov from the zero
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// register, because the immediate version of fmov cannot encode zero.
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if (CFP->isNullValue())
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@ -341,7 +341,7 @@ unsigned AArch64FastISel::AArch64MaterializeFP(const ConstantFP *CFP, MVT VT) {
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return ResultReg;
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}
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unsigned AArch64FastISel::AArch64MaterializeGV(const GlobalValue *GV) {
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unsigned AArch64FastISel::materializeGV(const GlobalValue *GV) {
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// We can't handle thread-local variables quickly yet.
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if (GV->isThreadLocal())
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return 0;
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@ -400,11 +400,11 @@ unsigned AArch64FastISel::fastMaterializeConstant(const Constant *C) {
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MVT VT = CEVT.getSimpleVT();
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if (const auto *CI = dyn_cast<ConstantInt>(C))
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return AArch64MaterializeInt(CI, VT);
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return materializeInt(CI, VT);
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else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
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return AArch64MaterializeFP(CFP, VT);
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return materializeFP(CFP, VT);
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else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
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return AArch64MaterializeGV(GV);
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return materializeGV(GV);
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return 0;
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}
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@ -426,7 +426,7 @@ unsigned AArch64FastISel::fastMaterializeFloatZero(const ConstantFP* CFP) {
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}
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// Computes the address to get to an object.
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bool AArch64FastISel::ComputeAddress(const Value *Obj, Address &Addr, Type *Ty)
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bool AArch64FastISel::computeAddress(const Value *Obj, Address &Addr, Type *Ty)
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{
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const User *U = nullptr;
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unsigned Opcode = Instruction::UserOp1;
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@ -454,18 +454,18 @@ bool AArch64FastISel::ComputeAddress(const Value *Obj, Address &Addr, Type *Ty)
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break;
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case Instruction::BitCast: {
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// Look through bitcasts.
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return ComputeAddress(U->getOperand(0), Addr, Ty);
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return computeAddress(U->getOperand(0), Addr, Ty);
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}
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case Instruction::IntToPtr: {
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// Look past no-op inttoptrs.
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if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
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return ComputeAddress(U->getOperand(0), Addr, Ty);
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return computeAddress(U->getOperand(0), Addr, Ty);
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break;
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}
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case Instruction::PtrToInt: {
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// Look past no-op ptrtoints.
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if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
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return ComputeAddress(U->getOperand(0), Addr, Ty);
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return computeAddress(U->getOperand(0), Addr, Ty);
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break;
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}
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case Instruction::GetElementPtr: {
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@ -507,7 +507,7 @@ bool AArch64FastISel::ComputeAddress(const Value *Obj, Address &Addr, Type *Ty)
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// Try to grab the base operand now.
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Addr.setOffset(TmpOffset);
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if (ComputeAddress(U->getOperand(0), Addr, Ty))
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if (computeAddress(U->getOperand(0), Addr, Ty))
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return true;
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// We failed, restore everything and try the other options.
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@ -537,11 +537,11 @@ bool AArch64FastISel::ComputeAddress(const Value *Obj, Address &Addr, Type *Ty)
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if (const ConstantInt *CI = dyn_cast<ConstantInt>(RHS)) {
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Addr.setOffset(Addr.getOffset() + (uint64_t)CI->getSExtValue());
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return ComputeAddress(LHS, Addr, Ty);
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return computeAddress(LHS, Addr, Ty);
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}
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Address Backup = Addr;
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if (ComputeAddress(LHS, Addr, Ty) && ComputeAddress(RHS, Addr, Ty))
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if (computeAddress(LHS, Addr, Ty) && computeAddress(RHS, Addr, Ty))
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return true;
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Addr = Backup;
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@ -609,7 +609,7 @@ bool AArch64FastISel::ComputeAddress(const Value *Obj, Address &Addr, Type *Ty)
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return true;
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}
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bool AArch64FastISel::ComputeCallAddress(const Value *V, Address &Addr) {
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bool AArch64FastISel::computeCallAddress(const Value *V, Address &Addr) {
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const User *U = nullptr;
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unsigned Opcode = Instruction::UserOp1;
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bool InMBB = true;
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@ -628,19 +628,19 @@ bool AArch64FastISel::ComputeCallAddress(const Value *V, Address &Addr) {
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case Instruction::BitCast:
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// Look past bitcasts if its operand is in the same BB.
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if (InMBB)
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return ComputeCallAddress(U->getOperand(0), Addr);
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return computeCallAddress(U->getOperand(0), Addr);
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break;
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case Instruction::IntToPtr:
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// Look past no-op inttoptrs if its operand is in the same BB.
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if (InMBB &&
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TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
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return ComputeCallAddress(U->getOperand(0), Addr);
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return computeCallAddress(U->getOperand(0), Addr);
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break;
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case Instruction::PtrToInt:
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// Look past no-op ptrtoints if its operand is in the same BB.
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if (InMBB &&
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TLI.getValueType(U->getType()) == TLI.getPointerTy())
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return ComputeCallAddress(U->getOperand(0), Addr);
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return computeCallAddress(U->getOperand(0), Addr);
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break;
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}
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@ -706,7 +706,7 @@ bool AArch64FastISel::isValueAvailable(const Value *V) const {
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return false;
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}
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bool AArch64FastISel::SimplifyAddress(Address &Addr, MVT VT) {
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bool AArch64FastISel::simplifyAddress(Address &Addr, MVT VT) {
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unsigned ScaleFactor;
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switch (VT.SimpleTy) {
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default: return false;
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@ -807,7 +807,7 @@ bool AArch64FastISel::SimplifyAddress(Address &Addr, MVT VT) {
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return true;
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}
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void AArch64FastISel::AddLoadStoreOperands(Address &Addr,
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void AArch64FastISel::addLoadStoreOperands(Address &Addr,
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const MachineInstrBuilder &MIB,
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unsigned Flags,
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unsigned ScaleFactor,
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@ -894,7 +894,7 @@ unsigned AArch64FastISel::emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
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bool LHSIsKill = hasTrivialKill(LHS);
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if (NeedExtend)
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LHSReg = EmitIntExt(SrcVT, LHSReg, RetVT, IsZExt);
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LHSReg = emitIntExt(SrcVT, LHSReg, RetVT, IsZExt);
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unsigned ResultReg = 0;
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if (const auto *C = dyn_cast<ConstantInt>(RHS)) {
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@ -960,7 +960,7 @@ unsigned AArch64FastISel::emitAddSub(bool UseAdd, MVT RetVT, const Value *LHS,
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bool RHSIsKill = hasTrivialKill(RHS);
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if (NeedExtend)
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RHSReg = EmitIntExt(SrcVT, RHSReg, RetVT, IsZExt);
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RHSReg = emitIntExt(SrcVT, RHSReg, RetVT, IsZExt);
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return emitAddSub_rr(UseAdd, RetVT, LHSReg, LHSIsKill, RHSReg, RHSIsKill,
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SetFlags, WantResult);
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@ -1363,10 +1363,10 @@ unsigned AArch64FastISel::emitAnd_ri(MVT RetVT, unsigned LHSReg, bool LHSIsKill,
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return emitLogicalOp_ri(ISD::AND, RetVT, LHSReg, LHSIsKill, Imm);
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}
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bool AArch64FastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
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bool AArch64FastISel::emitLoad(MVT VT, unsigned &ResultReg, Address Addr,
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MachineMemOperand *MMO) {
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// Simplify this down to something we can handle.
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if (!SimplifyAddress(Addr, VT))
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if (!simplifyAddress(Addr, VT))
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return false;
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unsigned ScaleFactor;
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@ -1425,7 +1425,7 @@ bool AArch64FastISel::EmitLoad(MVT VT, unsigned &ResultReg, Address Addr,
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ResultReg = createResultReg(RC);
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MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(Opc), ResultReg);
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AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOLoad, ScaleFactor, MMO);
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addLoadStoreOperands(Addr, MIB, MachineMemOperand::MOLoad, ScaleFactor, MMO);
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// Loading an i1 requires special handling.
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if (VTIsi1) {
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@ -1491,7 +1491,7 @@ bool AArch64FastISel::selectLogicalOp(const Instruction *I) {
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return true;
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}
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bool AArch64FastISel::SelectLoad(const Instruction *I) {
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bool AArch64FastISel::selectLoad(const Instruction *I) {
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MVT VT;
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// Verify we have a legal type before going any further. Currently, we handle
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// simple types that will directly fit in a register (i32/f32/i64/f64) or
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@ -1502,21 +1502,21 @@ bool AArch64FastISel::SelectLoad(const Instruction *I) {
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// See if we can handle this address.
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Address Addr;
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if (!ComputeAddress(I->getOperand(0), Addr, I->getType()))
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if (!computeAddress(I->getOperand(0), Addr, I->getType()))
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return false;
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unsigned ResultReg;
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if (!EmitLoad(VT, ResultReg, Addr, createMachineMemOperandFor(I)))
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if (!emitLoad(VT, ResultReg, Addr, createMachineMemOperandFor(I)))
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return false;
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updateValueMap(I, ResultReg);
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return true;
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}
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bool AArch64FastISel::EmitStore(MVT VT, unsigned SrcReg, Address Addr,
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bool AArch64FastISel::emitStore(MVT VT, unsigned SrcReg, Address Addr,
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MachineMemOperand *MMO) {
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// Simplify this down to something we can handle.
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if (!SimplifyAddress(Addr, VT))
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if (!simplifyAddress(Addr, VT))
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return false;
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unsigned ScaleFactor;
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@ -1583,12 +1583,12 @@ bool AArch64FastISel::EmitStore(MVT VT, unsigned SrcReg, Address Addr,
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SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs());
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MachineInstrBuilder MIB =
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(SrcReg);
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AddLoadStoreOperands(Addr, MIB, MachineMemOperand::MOStore, ScaleFactor, MMO);
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addLoadStoreOperands(Addr, MIB, MachineMemOperand::MOStore, ScaleFactor, MMO);
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return true;
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}
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bool AArch64FastISel::SelectStore(const Instruction *I) {
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bool AArch64FastISel::selectStore(const Instruction *I) {
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MVT VT;
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const Value *Op0 = I->getOperand(0);
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// Verify we have a legal type before going any further. Currently, we handle
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@ -1619,10 +1619,10 @@ bool AArch64FastISel::SelectStore(const Instruction *I) {
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// See if we can handle this address.
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Address Addr;
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if (!ComputeAddress(I->getOperand(1), Addr, I->getOperand(0)->getType()))
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if (!computeAddress(I->getOperand(1), Addr, I->getOperand(0)->getType()))
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return false;
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if (!EmitStore(VT, SrcReg, Addr, createMachineMemOperandFor(I)))
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if (!emitStore(VT, SrcReg, Addr, createMachineMemOperandFor(I)))
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return false;
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return true;
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}
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@ -1673,7 +1673,7 @@ static AArch64CC::CondCode getCompareCC(CmpInst::Predicate Pred) {
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}
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}
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bool AArch64FastISel::SelectBranch(const Instruction *I) {
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bool AArch64FastISel::selectBranch(const Instruction *I) {
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const BranchInst *BI = cast<BranchInst>(I);
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if (BI->isUnconditional()) {
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MachineBasicBlock *MSucc = FuncInfo.MBBMap[BI->getSuccessor(0)];
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||||
@ -1820,7 +1820,7 @@ bool AArch64FastISel::SelectBranch(const Instruction *I) {
|
||||
return true;
|
||||
}
|
||||
|
||||
bool AArch64FastISel::SelectIndirectBr(const Instruction *I) {
|
||||
bool AArch64FastISel::selectIndirectBr(const Instruction *I) {
|
||||
const IndirectBrInst *BI = cast<IndirectBrInst>(I);
|
||||
unsigned AddrReg = getRegForValue(BI->getOperand(0));
|
||||
if (AddrReg == 0)
|
||||
@ -1838,7 +1838,7 @@ bool AArch64FastISel::SelectIndirectBr(const Instruction *I) {
|
||||
return true;
|
||||
}
|
||||
|
||||
bool AArch64FastISel::SelectCmp(const Instruction *I) {
|
||||
bool AArch64FastISel::selectCmp(const Instruction *I) {
|
||||
const CmpInst *CI = cast<CmpInst>(I);
|
||||
|
||||
// Try to optimize or fold the cmp.
|
||||
@ -1918,7 +1918,7 @@ bool AArch64FastISel::SelectCmp(const Instruction *I) {
|
||||
return true;
|
||||
}
|
||||
|
||||
bool AArch64FastISel::SelectSelect(const Instruction *I) {
|
||||
bool AArch64FastISel::selectSelect(const Instruction *I) {
|
||||
const SelectInst *SI = cast<SelectInst>(I);
|
||||
|
||||
EVT DestEVT = TLI.getValueType(SI->getType(), true);
|
||||
@ -1976,7 +1976,7 @@ bool AArch64FastISel::SelectSelect(const Instruction *I) {
|
||||
return true;
|
||||
}
|
||||
|
||||
bool AArch64FastISel::SelectFPExt(const Instruction *I) {
|
||||
bool AArch64FastISel::selectFPExt(const Instruction *I) {
|
||||
Value *V = I->getOperand(0);
|
||||
if (!I->getType()->isDoubleTy() || !V->getType()->isFloatTy())
|
||||
return false;
|
||||
@ -1992,7 +1992,7 @@ bool AArch64FastISel::SelectFPExt(const Instruction *I) {
|
||||
return true;
|
||||
}
|
||||
|
||||
bool AArch64FastISel::SelectFPTrunc(const Instruction *I) {
|
||||
bool AArch64FastISel::selectFPTrunc(const Instruction *I) {
|
||||
Value *V = I->getOperand(0);
|
||||
if (!I->getType()->isFloatTy() || !V->getType()->isDoubleTy())
|
||||
return false;
|
||||
@ -2009,7 +2009,7 @@ bool AArch64FastISel::SelectFPTrunc(const Instruction *I) {
|
||||
}
|
||||
|
||||
// FPToUI and FPToSI
|
||||
bool AArch64FastISel::SelectFPToInt(const Instruction *I, bool Signed) {
|
||||
bool AArch64FastISel::selectFPToInt(const Instruction *I, bool Signed) {
|
||||
MVT DestVT;
|
||||
if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
|
||||
return false;
|
||||
@ -2042,7 +2042,7 @@ bool AArch64FastISel::SelectFPToInt(const Instruction *I, bool Signed) {
|
||||
return true;
|
||||
}
|
||||
|
||||
bool AArch64FastISel::SelectIntToFP(const Instruction *I, bool Signed) {
|
||||
bool AArch64FastISel::selectIntToFP(const Instruction *I, bool Signed) {
|
||||
MVT DestVT;
|
||||
if (!isTypeLegal(I->getType(), DestVT) || DestVT.isVector())
|
||||
return false;
|
||||
@ -2059,7 +2059,7 @@ bool AArch64FastISel::SelectIntToFP(const Instruction *I, bool Signed) {
|
||||
// Handle sign-extension.
|
||||
if (SrcVT == MVT::i16 || SrcVT == MVT::i8 || SrcVT == MVT::i1) {
|
||||
SrcReg =
|
||||
EmitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed);
|
||||
emitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed);
|
||||
if (!SrcReg)
|
||||
return false;
|
||||
SrcIsKill = true;
|
||||
@ -2191,7 +2191,7 @@ bool AArch64FastISel::fastLowerArguments() {
|
||||
return true;
|
||||
}
|
||||
|
||||
bool AArch64FastISel::ProcessCallArgs(CallLoweringInfo &CLI,
|
||||
bool AArch64FastISel::processCallArgs(CallLoweringInfo &CLI,
|
||||
SmallVectorImpl<MVT> &OutVTs,
|
||||
unsigned &NumBytes) {
|
||||
CallingConv::ID CC = CLI.CallConv;
|
||||
@ -2224,7 +2224,7 @@ bool AArch64FastISel::ProcessCallArgs(CallLoweringInfo &CLI,
|
||||
case CCValAssign::SExt: {
|
||||
MVT DestVT = VA.getLocVT();
|
||||
MVT SrcVT = ArgVT;
|
||||
ArgReg = EmitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
|
||||
ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/false);
|
||||
if (!ArgReg)
|
||||
return false;
|
||||
break;
|
||||
@ -2234,7 +2234,7 @@ bool AArch64FastISel::ProcessCallArgs(CallLoweringInfo &CLI,
|
||||
case CCValAssign::ZExt: {
|
||||
MVT DestVT = VA.getLocVT();
|
||||
MVT SrcVT = ArgVT;
|
||||
ArgReg = EmitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
|
||||
ArgReg = emitIntExt(SrcVT, ArgReg, DestVT, /*isZExt=*/true);
|
||||
if (!ArgReg)
|
||||
return false;
|
||||
break;
|
||||
@ -2275,14 +2275,14 @@ bool AArch64FastISel::ProcessCallArgs(CallLoweringInfo &CLI,
|
||||
MachinePointerInfo::getStack(Addr.getOffset()),
|
||||
MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment);
|
||||
|
||||
if (!EmitStore(ArgVT, ArgReg, Addr, MMO))
|
||||
if (!emitStore(ArgVT, ArgReg, Addr, MMO))
|
||||
return false;
|
||||
}
|
||||
}
|
||||
return true;
|
||||
}
|
||||
|
||||
bool AArch64FastISel::FinishCall(CallLoweringInfo &CLI, MVT RetVT,
|
||||
bool AArch64FastISel::finishCall(CallLoweringInfo &CLI, MVT RetVT,
|
||||
unsigned NumBytes) {
|
||||
CallingConv::ID CC = CLI.CallConv;
|
||||
|
||||
@ -2372,12 +2372,12 @@ bool AArch64FastISel::fastLowerCall(CallLoweringInfo &CLI) {
|
||||
}
|
||||
|
||||
Address Addr;
|
||||
if (Callee && !ComputeCallAddress(Callee, Addr))
|
||||
if (Callee && !computeCallAddress(Callee, Addr))
|
||||
return false;
|
||||
|
||||
// Handle the arguments now that we've gotten them.
|
||||
unsigned NumBytes;
|
||||
if (!ProcessCallArgs(CLI, OutVTs, NumBytes))
|
||||
if (!processCallArgs(CLI, OutVTs, NumBytes))
|
||||
return false;
|
||||
|
||||
// Issue the call.
|
||||
@ -2408,9 +2408,9 @@ bool AArch64FastISel::fastLowerCall(CallLoweringInfo &CLI) {
|
||||
.addReg(ADRPReg)
|
||||
.addExternalSymbol(SymName, AArch64II::MO_GOT | AArch64II::MO_PAGEOFF |
|
||||
AArch64II::MO_NC);
|
||||
} else if (Addr.getGlobalValue()) {
|
||||
CallReg = AArch64MaterializeGV(Addr.getGlobalValue());
|
||||
} else if (Addr.getReg())
|
||||
} else if (Addr.getGlobalValue())
|
||||
CallReg = materializeGV(Addr.getGlobalValue());
|
||||
else if (Addr.getReg())
|
||||
CallReg = Addr.getReg();
|
||||
|
||||
if (!CallReg)
|
||||
@ -2432,20 +2432,20 @@ bool AArch64FastISel::fastLowerCall(CallLoweringInfo &CLI) {
|
||||
CLI.Call = MIB;
|
||||
|
||||
// Finish off the call including any return values.
|
||||
return FinishCall(CLI, RetVT, NumBytes);
|
||||
return finishCall(CLI, RetVT, NumBytes);
|
||||
}
|
||||
|
||||
bool AArch64FastISel::IsMemCpySmall(uint64_t Len, unsigned Alignment) {
|
||||
bool AArch64FastISel::isMemCpySmall(uint64_t Len, unsigned Alignment) {
|
||||
if (Alignment)
|
||||
return Len / Alignment <= 4;
|
||||
else
|
||||
return Len < 32;
|
||||
}
|
||||
|
||||
bool AArch64FastISel::TryEmitSmallMemCpy(Address Dest, Address Src,
|
||||
bool AArch64FastISel::tryEmitSmallMemCpy(Address Dest, Address Src,
|
||||
uint64_t Len, unsigned Alignment) {
|
||||
// Make sure we don't bloat code by inlining very large memcpy's.
|
||||
if (!IsMemCpySmall(Len, Alignment))
|
||||
if (!isMemCpySmall(Len, Alignment))
|
||||
return false;
|
||||
|
||||
int64_t UnscaledOffset = 0;
|
||||
@ -2477,11 +2477,11 @@ bool AArch64FastISel::TryEmitSmallMemCpy(Address Dest, Address Src,
|
||||
|
||||
bool RV;
|
||||
unsigned ResultReg;
|
||||
RV = EmitLoad(VT, ResultReg, Src);
|
||||
RV = emitLoad(VT, ResultReg, Src);
|
||||
if (!RV)
|
||||
return false;
|
||||
|
||||
RV = EmitStore(VT, ResultReg, Dest);
|
||||
RV = emitStore(VT, ResultReg, Dest);
|
||||
if (!RV)
|
||||
return false;
|
||||
|
||||
@ -2601,12 +2601,12 @@ bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
|
||||
// if possible.
|
||||
uint64_t Len = cast<ConstantInt>(MTI->getLength())->getZExtValue();
|
||||
unsigned Alignment = MTI->getAlignment();
|
||||
if (IsMemCpySmall(Len, Alignment)) {
|
||||
if (isMemCpySmall(Len, Alignment)) {
|
||||
Address Dest, Src;
|
||||
if (!ComputeAddress(MTI->getRawDest(), Dest) ||
|
||||
!ComputeAddress(MTI->getRawSource(), Src))
|
||||
if (!computeAddress(MTI->getRawDest(), Dest) ||
|
||||
!computeAddress(MTI->getRawSource(), Src))
|
||||
return false;
|
||||
if (TryEmitSmallMemCpy(Dest, Src, Len, Alignment))
|
||||
if (tryEmitSmallMemCpy(Dest, Src, Len, Alignment))
|
||||
return true;
|
||||
}
|
||||
}
|
||||
@ -2770,7 +2770,7 @@ bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
|
||||
bool RHSIsKill = hasTrivialKill(RHS);
|
||||
|
||||
if (VT == MVT::i32) {
|
||||
MulReg = Emit_SMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
|
||||
MulReg = emitSMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
|
||||
unsigned ShiftReg = emitLSR_ri(MVT::i64, MVT::i64, MulReg,
|
||||
/*IsKill=*/false, 32);
|
||||
MulReg = fastEmitInst_extractsubreg(VT, MulReg, /*IsKill=*/true,
|
||||
@ -2781,7 +2781,7 @@ bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
|
||||
AArch64_AM::ASR, 31, /*WantResult=*/false);
|
||||
} else {
|
||||
assert(VT == MVT::i64 && "Unexpected value type.");
|
||||
MulReg = Emit_MUL_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
|
||||
MulReg = emitMul_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
|
||||
unsigned SMULHReg = fastEmit_rr(VT, VT, ISD::MULHS, LHSReg, LHSIsKill,
|
||||
RHSReg, RHSIsKill);
|
||||
emitSubs_rs(VT, SMULHReg, /*IsKill=*/true, MulReg, /*IsKill=*/false,
|
||||
@ -2802,7 +2802,7 @@ bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
|
||||
bool RHSIsKill = hasTrivialKill(RHS);
|
||||
|
||||
if (VT == MVT::i32) {
|
||||
MulReg = Emit_UMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
|
||||
MulReg = emitUMULL_rr(MVT::i64, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
|
||||
emitSubs_rs(MVT::i64, AArch64::XZR, /*IsKill=*/true, MulReg,
|
||||
/*IsKill=*/false, AArch64_AM::LSR, 32,
|
||||
/*WantResult=*/false);
|
||||
@ -2810,7 +2810,7 @@ bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
|
||||
AArch64::sub_32);
|
||||
} else {
|
||||
assert(VT == MVT::i64 && "Unexpected value type.");
|
||||
MulReg = Emit_MUL_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
|
||||
MulReg = emitMul_rr(VT, LHSReg, LHSIsKill, RHSReg, RHSIsKill);
|
||||
unsigned UMULHReg = fastEmit_rr(VT, VT, ISD::MULHU, LHSReg, LHSIsKill,
|
||||
RHSReg, RHSIsKill);
|
||||
emitSubs_rr(VT, AArch64::XZR, /*IsKill=*/true, UMULHReg,
|
||||
@ -2838,7 +2838,7 @@ bool AArch64FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) {
|
||||
return false;
|
||||
}
|
||||
|
||||
bool AArch64FastISel::SelectRet(const Instruction *I) {
|
||||
bool AArch64FastISel::selectRet(const Instruction *I) {
|
||||
const ReturnInst *Ret = cast<ReturnInst>(I);
|
||||
const Function &F = *I->getParent()->getParent();
|
||||
|
||||
@ -2906,8 +2906,8 @@ bool AArch64FastISel::SelectRet(const Instruction *I) {
|
||||
if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt())
|
||||
return false;
|
||||
|
||||
bool isZExt = Outs[0].Flags.isZExt();
|
||||
SrcReg = EmitIntExt(RVVT, SrcReg, DestVT, isZExt);
|
||||
bool IsZExt = Outs[0].Flags.isZExt();
|
||||
SrcReg = emitIntExt(RVVT, SrcReg, DestVT, IsZExt);
|
||||
if (SrcReg == 0)
|
||||
return false;
|
||||
}
|
||||
@ -2927,7 +2927,7 @@ bool AArch64FastISel::SelectRet(const Instruction *I) {
|
||||
return true;
|
||||
}
|
||||
|
||||
bool AArch64FastISel::SelectTrunc(const Instruction *I) {
|
||||
bool AArch64FastISel::selectTrunc(const Instruction *I) {
|
||||
Type *DestTy = I->getType();
|
||||
Value *Op = I->getOperand(0);
|
||||
Type *SrcTy = Op->getType();
|
||||
@ -2993,7 +2993,7 @@ bool AArch64FastISel::SelectTrunc(const Instruction *I) {
|
||||
return true;
|
||||
}
|
||||
|
||||
unsigned AArch64FastISel::Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt) {
|
||||
unsigned AArch64FastISel::emiti1Ext(unsigned SrcReg, MVT DestVT, bool IsZExt) {
|
||||
assert((DestVT == MVT::i8 || DestVT == MVT::i16 || DestVT == MVT::i32 ||
|
||||
DestVT == MVT::i64) &&
|
||||
"Unexpected value type.");
|
||||
@ -3001,7 +3001,7 @@ unsigned AArch64FastISel::Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt) {
|
||||
if (DestVT == MVT::i8 || DestVT == MVT::i16)
|
||||
DestVT = MVT::i32;
|
||||
|
||||
if (isZExt) {
|
||||
if (IsZExt) {
|
||||
unsigned ResultReg = emitAnd_ri(MVT::i32, SrcReg, /*TODO:IsKill=*/false, 1);
|
||||
assert(ResultReg && "Unexpected AND instruction emission failure.");
|
||||
if (DestVT == MVT::i64) {
|
||||
@ -3026,7 +3026,7 @@ unsigned AArch64FastISel::Emiti1Ext(unsigned SrcReg, MVT DestVT, bool isZExt) {
|
||||
}
|
||||
}
|
||||
|
||||
unsigned AArch64FastISel::Emit_MUL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
|
||||
unsigned AArch64FastISel::emitMul_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
|
||||
unsigned Op1, bool Op1IsKill) {
|
||||
unsigned Opc, ZReg;
|
||||
switch (RetVT.SimpleTy) {
|
||||
@ -3046,7 +3046,7 @@ unsigned AArch64FastISel::Emit_MUL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
|
||||
/*IsKill=*/ZReg, true);
|
||||
}
|
||||
|
||||
unsigned AArch64FastISel::Emit_SMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
|
||||
unsigned AArch64FastISel::emitSMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
|
||||
unsigned Op1, bool Op1IsKill) {
|
||||
if (RetVT != MVT::i64)
|
||||
return 0;
|
||||
@ -3056,7 +3056,7 @@ unsigned AArch64FastISel::Emit_SMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
|
||||
AArch64::XZR, /*IsKill=*/true);
|
||||
}
|
||||
|
||||
unsigned AArch64FastISel::Emit_UMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
|
||||
unsigned AArch64FastISel::emitUMULL_rr(MVT RetVT, unsigned Op0, bool Op0IsKill,
|
||||
unsigned Op1, bool Op1IsKill) {
|
||||
if (RetVT != MVT::i64)
|
||||
return 0;
|
||||
@ -3231,13 +3231,12 @@ unsigned AArch64FastISel::emitLSR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
|
||||
// 0b0000_0000_0000_0000__0000_0000_0000_0000 zext
|
||||
|
||||
if (Shift >= SrcBits && IsZExt)
|
||||
return AArch64MaterializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)),
|
||||
RetVT);
|
||||
return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT);
|
||||
|
||||
// It is not possible to fold a sign-extend into the LShr instruction. In this
|
||||
// case emit a sign-extend.
|
||||
if (!IsZExt) {
|
||||
Op0 = EmitIntExt(SrcVT, Op0, RetVT, IsZExt);
|
||||
Op0 = emitIntExt(SrcVT, Op0, RetVT, IsZExt);
|
||||
if (!Op0)
|
||||
return 0;
|
||||
Op0IsKill = true;
|
||||
@ -3284,7 +3283,7 @@ unsigned AArch64FastISel::emitASR_rr(MVT RetVT, unsigned Op0Reg, bool Op0IsKill,
|
||||
const TargetRegisterClass *RC =
|
||||
(RetVT == MVT::i64) ? &AArch64::GPR64RegClass : &AArch64::GPR32RegClass;
|
||||
if (NeedTrunc) {
|
||||
Op0Reg = EmitIntExt(RetVT, Op0Reg, MVT::i32, /*IsZExt=*/false);
|
||||
Op0Reg = emitIntExt(RetVT, Op0Reg, MVT::i32, /*IsZExt=*/false);
|
||||
Op1Reg = emitAnd_ri(MVT::i32, Op1Reg, Op1IsKill, Mask);
|
||||
Op0IsKill = Op1IsKill = true;
|
||||
}
|
||||
@ -3340,8 +3339,7 @@ unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
|
||||
// 0b0000_0000_0000_0000__0000_0000_0000_0000 zext
|
||||
|
||||
if (Shift >= SrcBits && IsZExt)
|
||||
return AArch64MaterializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)),
|
||||
RetVT);
|
||||
return materializeInt(ConstantInt::get(*Context, APInt(RegSize, 0)), RetVT);
|
||||
|
||||
unsigned ImmR = std::min<unsigned>(SrcBits - 1, Shift);
|
||||
unsigned ImmS = SrcBits - 1;
|
||||
@ -3365,8 +3363,8 @@ unsigned AArch64FastISel::emitASR_ri(MVT RetVT, MVT SrcVT, unsigned Op0,
|
||||
return fastEmitInst_rii(Opc, RC, Op0, Op0IsKill, ImmR, ImmS);
|
||||
}
|
||||
|
||||
unsigned AArch64FastISel::EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
|
||||
bool isZExt) {
|
||||
unsigned AArch64FastISel::emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
|
||||
bool IsZExt) {
|
||||
assert(DestVT != MVT::i1 && "ZeroExt/SignExt an i1?");
|
||||
|
||||
// FastISel does not have plumbing to deal with extensions where the SrcVT or
|
||||
@ -3386,24 +3384,24 @@ unsigned AArch64FastISel::EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
|
||||
default:
|
||||
return 0;
|
||||
case MVT::i1:
|
||||
return Emiti1Ext(SrcReg, DestVT, isZExt);
|
||||
return emiti1Ext(SrcReg, DestVT, IsZExt);
|
||||
case MVT::i8:
|
||||
if (DestVT == MVT::i64)
|
||||
Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
|
||||
Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
|
||||
else
|
||||
Opc = isZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
|
||||
Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
|
||||
Imm = 7;
|
||||
break;
|
||||
case MVT::i16:
|
||||
if (DestVT == MVT::i64)
|
||||
Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
|
||||
Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
|
||||
else
|
||||
Opc = isZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
|
||||
Opc = IsZExt ? AArch64::UBFMWri : AArch64::SBFMWri;
|
||||
Imm = 15;
|
||||
break;
|
||||
case MVT::i32:
|
||||
assert(DestVT == MVT::i64 && "IntExt i32 to i32?!?");
|
||||
Opc = isZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
|
||||
Opc = IsZExt ? AArch64::UBFMXri : AArch64::SBFMXri;
|
||||
Imm = 31;
|
||||
break;
|
||||
}
|
||||
@ -3426,7 +3424,7 @@ unsigned AArch64FastISel::EmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
|
||||
return fastEmitInst_rii(Opc, RC, SrcReg, /*TODO:IsKill=*/false, 0, Imm);
|
||||
}
|
||||
|
||||
bool AArch64FastISel::SelectIntExt(const Instruction *I) {
|
||||
bool AArch64FastISel::selectIntExt(const Instruction *I) {
|
||||
// On ARM, in general, integer casts don't involve legal types; this code
|
||||
// handles promotable integers. The high bits for a type smaller than
|
||||
// the register size are assumed to be undefined.
|
||||
@ -3434,7 +3432,6 @@ bool AArch64FastISel::SelectIntExt(const Instruction *I) {
|
||||
Value *Src = I->getOperand(0);
|
||||
Type *SrcTy = Src->getType();
|
||||
|
||||
bool isZExt = isa<ZExtInst>(I);
|
||||
unsigned SrcReg = getRegForValue(Src);
|
||||
if (!SrcReg)
|
||||
return false;
|
||||
@ -3450,9 +3447,10 @@ bool AArch64FastISel::SelectIntExt(const Instruction *I) {
|
||||
MVT DestVT = DestEVT.getSimpleVT();
|
||||
unsigned ResultReg = 0;
|
||||
|
||||
bool IsZExt = isa<ZExtInst>(I);
|
||||
// Check if it is an argument and if it is already zero/sign-extended.
|
||||
if (const auto *Arg = dyn_cast<Argument>(Src)) {
|
||||
if ((isZExt && Arg->hasZExtAttr()) || (!isZExt && Arg->hasSExtAttr())) {
|
||||
if ((IsZExt && Arg->hasZExtAttr()) || (!IsZExt && Arg->hasSExtAttr())) {
|
||||
if (DestVT == MVT::i64) {
|
||||
ResultReg = createResultReg(TLI.getRegClassFor(DestVT));
|
||||
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
|
||||
@ -3466,7 +3464,7 @@ bool AArch64FastISel::SelectIntExt(const Instruction *I) {
|
||||
}
|
||||
|
||||
if (!ResultReg)
|
||||
ResultReg = EmitIntExt(SrcVT, SrcReg, DestVT, isZExt);
|
||||
ResultReg = emitIntExt(SrcVT, SrcReg, DestVT, IsZExt);
|
||||
|
||||
if (!ResultReg)
|
||||
return false;
|
||||
@ -3475,7 +3473,7 @@ bool AArch64FastISel::SelectIntExt(const Instruction *I) {
|
||||
return true;
|
||||
}
|
||||
|
||||
bool AArch64FastISel::SelectRem(const Instruction *I, unsigned ISDOpcode) {
|
||||
bool AArch64FastISel::selectRem(const Instruction *I, unsigned ISDOpcode) {
|
||||
EVT DestEVT = TLI.getValueType(I->getType(), true);
|
||||
if (!DestEVT.isSimple())
|
||||
return false;
|
||||
@ -3485,18 +3483,18 @@ bool AArch64FastISel::SelectRem(const Instruction *I, unsigned ISDOpcode) {
|
||||
return false;
|
||||
|
||||
unsigned DivOpc;
|
||||
bool is64bit = (DestVT == MVT::i64);
|
||||
bool Is64bit = (DestVT == MVT::i64);
|
||||
switch (ISDOpcode) {
|
||||
default:
|
||||
return false;
|
||||
case ISD::SREM:
|
||||
DivOpc = is64bit ? AArch64::SDIVXr : AArch64::SDIVWr;
|
||||
DivOpc = Is64bit ? AArch64::SDIVXr : AArch64::SDIVWr;
|
||||
break;
|
||||
case ISD::UREM:
|
||||
DivOpc = is64bit ? AArch64::UDIVXr : AArch64::UDIVWr;
|
||||
DivOpc = Is64bit ? AArch64::UDIVXr : AArch64::UDIVWr;
|
||||
break;
|
||||
}
|
||||
unsigned MSubOpc = is64bit ? AArch64::MSUBXrrr : AArch64::MSUBWrrr;
|
||||
unsigned MSubOpc = Is64bit ? AArch64::MSUBXrrr : AArch64::MSUBWrrr;
|
||||
unsigned Src0Reg = getRegForValue(I->getOperand(0));
|
||||
if (!Src0Reg)
|
||||
return false;
|
||||
@ -3521,7 +3519,7 @@ bool AArch64FastISel::SelectRem(const Instruction *I, unsigned ISDOpcode) {
|
||||
return true;
|
||||
}
|
||||
|
||||
bool AArch64FastISel::SelectMul(const Instruction *I) {
|
||||
bool AArch64FastISel::selectMul(const Instruction *I) {
|
||||
EVT SrcEVT = TLI.getValueType(I->getOperand(0)->getType(), true);
|
||||
if (!SrcEVT.isSimple())
|
||||
return false;
|
||||
@ -3543,7 +3541,7 @@ bool AArch64FastISel::SelectMul(const Instruction *I) {
|
||||
bool Src1IsKill = hasTrivialKill(I->getOperand(1));
|
||||
|
||||
unsigned ResultReg =
|
||||
Emit_MUL_rr(SrcVT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill);
|
||||
emitMul_rr(SrcVT, Src0Reg, Src0IsKill, Src1Reg, Src1IsKill);
|
||||
|
||||
if (!ResultReg)
|
||||
return false;
|
||||
@ -3552,7 +3550,7 @@ bool AArch64FastISel::SelectMul(const Instruction *I) {
|
||||
return true;
|
||||
}
|
||||
|
||||
bool AArch64FastISel::SelectShift(const Instruction *I) {
|
||||
bool AArch64FastISel::selectShift(const Instruction *I) {
|
||||
MVT RetVT;
|
||||
if (!isTypeSupported(I->getType(), RetVT, /*IsVectorAllowed=*/true))
|
||||
return false;
|
||||
@ -3637,7 +3635,7 @@ bool AArch64FastISel::SelectShift(const Instruction *I) {
|
||||
return true;
|
||||
}
|
||||
|
||||
bool AArch64FastISel::SelectBitCast(const Instruction *I) {
|
||||
bool AArch64FastISel::selectBitCast(const Instruction *I) {
|
||||
MVT RetVT, SrcVT;
|
||||
|
||||
if (!isTypeLegal(I->getOperand(0)->getType(), SrcVT))
|
||||
@ -3724,71 +3722,71 @@ bool AArch64FastISel::fastSelectInstruction(const Instruction *I) {
|
||||
return selectAddSub(I);
|
||||
case Instruction::Mul:
|
||||
if (!selectBinaryOp(I, ISD::MUL))
|
||||
return SelectMul(I);
|
||||
return selectMul(I);
|
||||
return true;
|
||||
case Instruction::SRem:
|
||||
if (!selectBinaryOp(I, ISD::SREM))
|
||||
return SelectRem(I, ISD::SREM);
|
||||
return selectRem(I, ISD::SREM);
|
||||
return true;
|
||||
case Instruction::URem:
|
||||
if (!selectBinaryOp(I, ISD::UREM))
|
||||
return SelectRem(I, ISD::UREM);
|
||||
return selectRem(I, ISD::UREM);
|
||||
return true;
|
||||
case Instruction::Shl:
|
||||
case Instruction::LShr:
|
||||
case Instruction::AShr:
|
||||
return SelectShift(I);
|
||||
return selectShift(I);
|
||||
case Instruction::And:
|
||||
case Instruction::Or:
|
||||
case Instruction::Xor:
|
||||
return selectLogicalOp(I);
|
||||
case Instruction::Br:
|
||||
return SelectBranch(I);
|
||||
return selectBranch(I);
|
||||
case Instruction::IndirectBr:
|
||||
return SelectIndirectBr(I);
|
||||
return selectIndirectBr(I);
|
||||
case Instruction::BitCast:
|
||||
if (!FastISel::selectBitCast(I))
|
||||
return SelectBitCast(I);
|
||||
return selectBitCast(I);
|
||||
return true;
|
||||
case Instruction::FPToSI:
|
||||
if (!selectCast(I, ISD::FP_TO_SINT))
|
||||
return SelectFPToInt(I, /*Signed=*/true);
|
||||
return selectFPToInt(I, /*Signed=*/true);
|
||||
return true;
|
||||
case Instruction::FPToUI:
|
||||
return SelectFPToInt(I, /*Signed=*/false);
|
||||
return selectFPToInt(I, /*Signed=*/false);
|
||||
case Instruction::ZExt:
|
||||
if (!selectCast(I, ISD::ZERO_EXTEND))
|
||||
return SelectIntExt(I);
|
||||
return selectIntExt(I);
|
||||
return true;
|
||||
case Instruction::SExt:
|
||||
if (!selectCast(I, ISD::SIGN_EXTEND))
|
||||
return SelectIntExt(I);
|
||||
return selectIntExt(I);
|
||||
return true;
|
||||
case Instruction::Trunc:
|
||||
if (!selectCast(I, ISD::TRUNCATE))
|
||||
return SelectTrunc(I);
|
||||
return selectTrunc(I);
|
||||
return true;
|
||||
case Instruction::FPExt:
|
||||
return SelectFPExt(I);
|
||||
return selectFPExt(I);
|
||||
case Instruction::FPTrunc:
|
||||
return SelectFPTrunc(I);
|
||||
return selectFPTrunc(I);
|
||||
case Instruction::SIToFP:
|
||||
if (!selectCast(I, ISD::SINT_TO_FP))
|
||||
return SelectIntToFP(I, /*Signed=*/true);
|
||||
return selectIntToFP(I, /*Signed=*/true);
|
||||
return true;
|
||||
case Instruction::UIToFP:
|
||||
return SelectIntToFP(I, /*Signed=*/false);
|
||||
return selectIntToFP(I, /*Signed=*/false);
|
||||
case Instruction::Load:
|
||||
return SelectLoad(I);
|
||||
return selectLoad(I);
|
||||
case Instruction::Store:
|
||||
return SelectStore(I);
|
||||
return selectStore(I);
|
||||
case Instruction::FCmp:
|
||||
case Instruction::ICmp:
|
||||
return SelectCmp(I);
|
||||
return selectCmp(I);
|
||||
case Instruction::Select:
|
||||
return SelectSelect(I);
|
||||
return selectSelect(I);
|
||||
case Instruction::Ret:
|
||||
return SelectRet(I);
|
||||
return selectRet(I);
|
||||
case Instruction::FRem:
|
||||
return selectFRem(I);
|
||||
}
|
||||
@ -3800,8 +3798,8 @@ bool AArch64FastISel::fastSelectInstruction(const Instruction *I) {
|
||||
}
|
||||
|
||||
namespace llvm {
|
||||
llvm::FastISel *AArch64::createFastISel(FunctionLoweringInfo &funcInfo,
|
||||
const TargetLibraryInfo *libInfo) {
|
||||
return new AArch64FastISel(funcInfo, libInfo);
|
||||
llvm::FastISel *AArch64::createFastISel(FunctionLoweringInfo &FuncInfo,
|
||||
const TargetLibraryInfo *LibInfo) {
|
||||
return new AArch64FastISel(FuncInfo, LibInfo);
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user