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Finish fixing the MachineOperand hashing, providing a nice modern
hash_value overload for MachineOperands. This addresses a FIXME sufficient for me to remove it, and cleans up the code nicely too. The important changes to the hashing logic: - TargetFlags are now included in all of the hashes. These were complete missed. - Register operands have their subregisters and whether they are a def included in the hash. - We now actually hash all of the operand types. Previously, many operand types were simply *dropped on the floor*. For example: - Floating point immediates - Large integer immediates (>64-bit) - External globals! - Register masks - Metadata operands - It removes the offset from the block-address hash; I'm a bit suspicious of this, but isIdenticalTo doesn't consider the offset for black addresses. Any patterns involving these entities could have triggered extreme slowdowns in MachineCSE or PHIElimination. Let me know if there are PRs you think might be closed now... I'm looking myself, but I may miss them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159743 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chandler Carruth
parent
483c54b811
commit
d862d697d2
@ -14,6 +14,7 @@
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#ifndef LLVM_CODEGEN_MACHINEOPERAND_H
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#define LLVM_CODEGEN_MACHINEOPERAND_H
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#include "llvm/ADT/Hashing.h"
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#include "llvm/Support/DataTypes.h"
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#include <cassert>
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@ -503,6 +504,13 @@ public:
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/// operand. Note: This method ignores isKill and isDead properties.
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bool isIdenticalTo(const MachineOperand &Other) const;
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/// \brief MachineOperand hash_value overload.
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///
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/// Note that this includes the same information in the hash that
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/// isIdenticalTo uses for comparison. It is thus suited for use in hash
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/// tables which use that function for equality comparisons only.
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friend hash_code hash_value(const MachineOperand &MO);
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/// ChangeToImmediate - Replace this operand with a new immediate operand of
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/// the specified value. If an operand is known to be an immediate already,
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/// the setImm method should be used.
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@ -186,7 +186,8 @@ void MachineOperand::ChangeToRegister(unsigned Reg, bool isDef, bool isImp,
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}
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/// isIdenticalTo - Return true if this operand is identical to the specified
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/// operand.
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/// operand. Note that this should stay in sync with the hash_value overload
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/// below.
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bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
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if (getType() != Other.getType() ||
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getTargetFlags() != Other.getTargetFlags())
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@ -227,6 +228,46 @@ bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
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llvm_unreachable("Invalid machine operand type");
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}
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// Note: this must stay exactly in sync with isIdenticalTo above.
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hash_code llvm::hash_value(const MachineOperand &MO) {
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switch (MO.getType()) {
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case MachineOperand::MO_Register:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getReg(),
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MO.getSubReg(), MO.isDef());
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case MachineOperand::MO_Immediate:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getImm());
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case MachineOperand::MO_CImmediate:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCImm());
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case MachineOperand::MO_FPImmediate:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getFPImm());
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case MachineOperand::MO_MachineBasicBlock:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMBB());
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case MachineOperand::MO_FrameIndex:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
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case MachineOperand::MO_ConstantPoolIndex:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex(),
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MO.getOffset());
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case MachineOperand::MO_JumpTableIndex:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getIndex());
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case MachineOperand::MO_ExternalSymbol:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getOffset(),
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MO.getSymbolName());
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case MachineOperand::MO_GlobalAddress:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getGlobal(),
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MO.getOffset());
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case MachineOperand::MO_BlockAddress:
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return hash_combine(MO.getType(), MO.getTargetFlags(),
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MO.getBlockAddress());
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case MachineOperand::MO_RegisterMask:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getRegMask());
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case MachineOperand::MO_Metadata:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
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case MachineOperand::MO_MCSymbol:
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return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
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}
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llvm_unreachable("Invalid machine operand type");
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}
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/// print - Print the specified machine operand.
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///
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void MachineOperand::print(raw_ostream &OS, const TargetMachine *TM) const {
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@ -1854,57 +1895,16 @@ void MachineInstr::setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
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unsigned
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MachineInstrExpressionTrait::getHashValue(const MachineInstr* const &MI) {
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// Build up a buffer of hash code components.
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//
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// FIXME: This is a total hack. We should have a hash_value overload for
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// MachineOperand, but currently that doesn't work because there are many
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// different ideas of "equality" and thus different sets of information that
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// contribute to the hash code. This one happens to want to take a specific
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// subset. And it's still not clear that this routine uses the *correct*
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// subset of information when computing the hash code. The goal is to use the
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// same inputs for the hash code here that MachineInstr::isIdenticalTo uses to
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// test for equality when passed the 'IgnoreVRegDefs' filter flag. It would
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// be very useful to factor the selection of relevant inputs out of the two
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// functions and into a common routine, but it's not clear how that can be
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// done.
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SmallVector<size_t, 8> HashComponents;
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HashComponents.reserve(MI->getNumOperands() + 1);
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HashComponents.push_back(MI->getOpcode());
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI->getOperand(i);
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switch (MO.getType()) {
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default: break;
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case MachineOperand::MO_Register:
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if (MO.isDef() && TargetRegisterInfo::isVirtualRegister(MO.getReg()))
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continue; // Skip virtual register defs.
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HashComponents.push_back(hash_combine(MO.getType(), MO.getReg()));
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break;
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case MachineOperand::MO_Immediate:
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HashComponents.push_back(hash_combine(MO.getType(), MO.getImm()));
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break;
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case MachineOperand::MO_FrameIndex:
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case MachineOperand::MO_JumpTableIndex:
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HashComponents.push_back(hash_combine(MO.getType(), MO.getIndex()));
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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HashComponents.push_back(hash_combine(MO.getType(), MO.getIndex(),
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MO.getOffset()));
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break;
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case MachineOperand::MO_MachineBasicBlock:
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HashComponents.push_back(hash_combine(MO.getType(), MO.getMBB()));
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break;
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case MachineOperand::MO_GlobalAddress:
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HashComponents.push_back(hash_combine(MO.getType(), MO.getGlobal(),
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MO.getOffset()));
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break;
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case MachineOperand::MO_BlockAddress:
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HashComponents.push_back(hash_combine(MO.getType(),
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MO.getBlockAddress(),
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MO.getOffset()));
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break;
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case MachineOperand::MO_MCSymbol:
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HashComponents.push_back(hash_combine(MO.getType(), MO.getMCSymbol()));
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break;
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}
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if (MO.isReg() && MO.isDef() &&
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TargetRegisterInfo::isVirtualRegister(MO.getReg()))
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continue; // Skip virtual register defs.
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HashComponents.push_back(hash_value(MO));
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}
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return hash_combine_range(HashComponents.begin(), HashComponents.end());
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}
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