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Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58800 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2008-11-06 08:47:38 +00:00
parent 4c3a1d8d2b
commit d87293ce78
6 changed files with 228 additions and 234 deletions
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4
lib/Target/ARM/ARM.td
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@@ -101,15 +101,13 @@ def ARMInstrInfo : InstrInfo {
let TSFlagsFields = ["AddrModeBits", let TSFlagsFields = ["AddrModeBits",
"SizeFlag", "SizeFlag",
"IndexModeBits", "IndexModeBits",
"Opcode",
"isUnaryDataProc", "isUnaryDataProc",
"Form"]; "Form"];
let TSFlagsShifts = [0, let TSFlagsShifts = [0,
4, 4,
7, 7,
9, 9,
13, 10];
14];
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//

18
lib/Target/ARM/ARMCodeEmitter.cpp
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@@ -115,12 +115,6 @@ namespace {
return getMachineOpValue(MI, MI.getOperand(OpIdx)); return getMachineOpValue(MI, MI.getOperand(OpIdx));
} }
/// getBaseOpcodeFor - Return the opcode value.
///
unsigned getBaseOpcodeFor(const TargetInstrDesc &TID) const {
return (TID.TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
}
/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value. /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
/// ///
unsigned getShiftOp(unsigned Imm) const ; unsigned getShiftOp(unsigned Imm) const ;
@@ -531,6 +525,10 @@ void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
++OpIdx; ++OpIdx;
} }
// If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
++OpIdx;
// Encode first non-shifter register operand if there is one. // Encode first non-shifter register operand if there is one.
bool isUnary = TID.TSFlags & ARMII::UnaryDP; bool isUnary = TID.TSFlags & ARMII::UnaryDP;
if (!isUnary) { if (!isUnary) {
@@ -591,7 +589,7 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
} }
const MachineOperand &MO2 = MI.getOperand(OpIdx); const MachineOperand &MO2 = MI.getOperand(OpIdx);
unsigned AM2Opc = (OpIdx == TID.getNumOperands()) unsigned AM2Opc = (ImplicitRn == ARM::PC)
? 0 : MI.getOperand(OpIdx+1).getImm(); ? 0 : MI.getOperand(OpIdx+1).getImm();
// Set bit U(23) according to sign of immed value (positive or negative). // Set bit U(23) according to sign of immed value (positive or negative).
@@ -646,7 +644,7 @@ void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
} }
const MachineOperand &MO2 = MI.getOperand(OpIdx); const MachineOperand &MO2 = MI.getOperand(OpIdx);
unsigned AM3Opc = (OpIdx == TID.getNumOperands()) unsigned AM3Opc = (ImplicitRn == ARM::PC)
? 0 : MI.getOperand(OpIdx+1).getImm(); ? 0 : MI.getOperand(OpIdx+1).getImm();
// Set bit U(23) according to sign of immed value (positive or negative) // Set bit U(23) according to sign of immed value (positive or negative)
@@ -661,9 +659,9 @@ void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
return; return;
} }
// if this instr is in immediate offset/index encoding, set bit 22 to 1 // This instr is in immediate offset/index encoding, set bit 22 to 1.
Binary |= 1 << 22;
if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) { if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
Binary |= 1 << 22;
// Set operands // Set operands
Binary |= (ImmOffs >> 4) << 8; // immedH Binary |= (ImmOffs >> 4) << 8; // immedH
Binary |= (ImmOffs & ~0xF); // immedL Binary |= (ImmOffs & ~0xF); // immedL

249
lib/Target/ARM/ARMInstrFormats.td
View File

@@ -47,15 +47,13 @@ class UnaryDP { bit isUnaryDataProc = 1; }
// ARM Instruction templates. // ARM Instruction templates.
// //
class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im, class InstARM<AddrMode am, SizeFlagVal sz, IndexMode im,
Format f, string cstr> Format f, string cstr>
: Instruction { : Instruction {
field bits<32> Inst; field bits<32> Inst;
let Namespace = "ARM"; let Namespace = "ARM";
bits<4> Opcode = opcod;
// TSFlagsFields // TSFlagsFields
AddrMode AM = am; AddrMode AM = am;
bits<4> AddrModeBits = AM.Value; bits<4> AddrModeBits = AM.Value;
@@ -78,7 +76,7 @@ class InstARM<bits<4> opcod, AddrMode am, SizeFlagVal sz, IndexMode im,
} }
class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern> class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
: InstARM<0, AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> { : InstARM<AddrModeNone, SizeSpecial, IndexModeNone, Pseudo, ""> {
let OutOperandList = oops; let OutOperandList = oops;
let InOperandList = iops; let InOperandList = iops;
let AsmString = asm; let AsmString = asm;
@@ -86,10 +84,10 @@ class PseudoInst<dag oops, dag iops, string asm, list<dag> pattern>
} }
// Almost all ARM instructions are predicable. // Almost all ARM instructions are predicable.
class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, class I<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
IndexMode im, Format f, string opc, string asm, string cstr, IndexMode im, Format f, string opc, string asm, string cstr,
list<dag> pattern> list<dag> pattern>
: InstARM<opcod, am, sz, im, f, cstr> { : InstARM<am, sz, im, f, cstr> {
let OutOperandList = oops; let OutOperandList = oops;
let InOperandList = !con(iops, (ops pred:$p)); let InOperandList = !con(iops, (ops pred:$p));
let AsmString = !strconcat(opc, !strconcat("${p}", asm)); let AsmString = !strconcat(opc, !strconcat("${p}", asm));
@@ -100,10 +98,10 @@ class I<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
// Same as I except it can optionally modify CPSR. Note it's modeled as // Same as I except it can optionally modify CPSR. Note it's modeled as
// an input operand since by default it's a zero register. It will // an input operand since by default it's a zero register. It will
// become an implicit def once it's "flipped". // become an implicit def once it's "flipped".
class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, class sI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
IndexMode im, Format f, string opc, string asm, string cstr, IndexMode im, Format f, string opc, string asm, string cstr,
list<dag> pattern> list<dag> pattern>
: InstARM<opcod, am, sz, im, f, cstr> { : InstARM<am, sz, im, f, cstr> {
let OutOperandList = oops; let OutOperandList = oops;
let InOperandList = !con(iops, (ops pred:$p, cc_out:$s)); let InOperandList = !con(iops, (ops pred:$p, cc_out:$s));
let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm)); let AsmString = !strconcat(opc, !strconcat("${p}${s}", asm));
@@ -112,9 +110,9 @@ class sI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
} }
// Special cases // Special cases
class XI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz, class XI<dag oops, dag iops, AddrMode am, SizeFlagVal sz,
IndexMode im, Format f, string asm, string cstr, list<dag> pattern> IndexMode im, Format f, string asm, string cstr, list<dag> pattern>
: InstARM<opcod, am, sz, im, f, cstr> { : InstARM<am, sz, im, f, cstr> {
let OutOperandList = oops; let OutOperandList = oops;
let InOperandList = iops; let InOperandList = iops;
let AsmString = asm; let AsmString = asm;
@@ -122,46 +120,46 @@ class XI<bits<4> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
list<Predicate> Predicates = [IsARM]; list<Predicate> Predicates = [IsARM];
} }
class AI<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI<dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern> string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc, : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
asm,"",pattern>; asm,"",pattern>;
class AsI<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AsI<dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern> string asm, list<dag> pattern>
: sI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc, : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
asm,"",pattern>; asm,"",pattern>;
class AXI<bits<4> opcod, dag oops, dag iops, Format f, string asm, class AXI<dag oops, dag iops, Format f, string asm,
list<dag> pattern> list<dag> pattern>
: XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm, : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
"", pattern>; "", pattern>;
// Ctrl flow instructions // Ctrl flow instructions
class ABLpredI<bits<4> opcod, dag oops, dag iops, Format f, string opc, class ABLpredI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern> string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc, : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
asm,"",pattern> { asm,"",pattern> {
let Inst{27-24} = opcod; let Inst{27-24} = opcod;
} }
class ABLI<bits<4> opcod, dag oops, dag iops, Format f, string asm, class ABLI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
list<dag> pattern> list<dag> pattern>
: XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm, : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
"", pattern> { "", pattern> {
let Inst{27-24} = opcod; let Inst{27-24} = opcod;
} }
// FIXME: BX // FIXME: BX
class AXIx2<bits<4> opcod, dag oops, dag iops, Format f, string asm, class AXIx2<dag oops, dag iops, Format f, string asm,
list<dag> pattern> list<dag> pattern>
: XI<opcod, oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, f, asm, : XI<oops, iops, AddrModeNone, Size8Bytes, IndexModeNone, f, asm,
"", pattern>; "", pattern>;
class ABI<bits<4> opcod, dag oops, dag iops, Format f, string asm, class ABI<bits<4> opcod, dag oops, dag iops, Format f, string asm,
list<dag> pattern> list<dag> pattern>
: XI<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm, : XI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, asm,
"", pattern> { "", pattern> {
let Inst{27-24} = opcod; let Inst{27-24} = opcod;
} }
class ABccI<bits<4> opcod, dag oops, dag iops, Format f, string opc, class ABccI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern> string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc, : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, f, opc,
asm,"",pattern> { asm,"",pattern> {
let Inst{27-24} = opcod; let Inst{27-24} = opcod;
} }
@@ -169,7 +167,7 @@ class ABccI<bits<4> opcod, dag oops, dag iops, Format f, string opc,
// BR_JT instructions // BR_JT instructions
// == mov pc // == mov pc
class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern> class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
: XI<opcod, oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc, : XI<oops, iops, AddrModeNone, SizeSpecial, IndexModeNone, BranchMisc,
asm, "", pattern> { asm, "", pattern> {
let Inst{20} = 0; // S Bit let Inst{20} = 0; // S Bit
let Inst{24-21} = opcod; let Inst{24-21} = opcod;
@@ -177,7 +175,7 @@ class JTI<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
} }
// == add pc // == add pc
class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern> class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
: XI<opcod, oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc, : XI<oops, iops, AddrMode1, SizeSpecial, IndexModeNone, BranchMisc,
asm, "", pattern> { asm, "", pattern> {
let Inst{20} = 0; // S bit let Inst{20} = 0; // S bit
let Inst{24-21} = opcod; let Inst{24-21} = opcod;
@@ -185,7 +183,7 @@ class JTI1<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
} }
// == ldr pc // == ldr pc
class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern> class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
: XI<opcod, oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc, : XI<oops, iops, AddrMode2, SizeSpecial, IndexModeNone, BranchMisc,
asm, "", pattern> { asm, "", pattern> {
let Inst{20} = 1; // L bit let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
@@ -198,43 +196,43 @@ class JTI2<bits<4> opcod, dag oops, dag iops, string asm, list<dag> pattern>
// addrmode1 instructions // addrmode1 instructions
class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern> string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc, : I<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern> { asm, "", pattern> {
let Inst{24-21} = opcod; let Inst{24-21} = opcod;
let Inst{27-26} = {0,0}; let Inst{27-26} = {0,0};
} }
class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AsI1<bits<4> opcod, dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern> string asm, list<dag> pattern>
: sI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc, : sI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern> { asm, "", pattern> {
let Inst{24-21} = opcod; let Inst{24-21} = opcod;
let Inst{27-26} = {0,0}; let Inst{27-26} = {0,0};
} }
class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm, class AXI1<bits<4> opcod, dag oops, dag iops, Format f, string asm,
list<dag> pattern> list<dag> pattern>
: XI<opcod, oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm, : XI<oops, iops, AddrMode1, Size4Bytes, IndexModeNone, f, asm,
"", pattern> { "", pattern> {
let Inst{24-21} = opcod; let Inst{24-21} = opcod;
let Inst{27-26} = {0,0}; let Inst{27-26} = {0,0};
} }
class AI1x2<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI1x2<dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern> string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc, : I<oops, iops, AddrMode1, Size8Bytes, IndexModeNone, f, opc,
asm, "", pattern>; asm, "", pattern>;
// addrmode2 loads and stores // addrmode2 loads and stores
class AI2<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI2<dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern> string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern> { asm, "", pattern> {
let Inst{27-26} = {0,1}; let Inst{27-26} = {0,1};
} }
// loads // loads
class AI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI2ldw<dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern> string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern> { asm, "", pattern> {
let Inst{20} = 1; // L bit let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
@@ -242,9 +240,9 @@ class AI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
let Inst{27-26} = {0,1}; let Inst{27-26} = {0,1};
} }
class AXI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string asm, class AXI2ldw<dag oops, dag iops, Format f, string asm,
list<dag> pattern> list<dag> pattern>
: XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
asm, "", pattern> { asm, "", pattern> {
let Inst{20} = 1; // L bit let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
@@ -252,9 +250,9 @@ class AXI2ldw<bits<4> opcod, dag oops, dag iops, Format f, string asm,
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
let Inst{27-26} = {0,1}; let Inst{27-26} = {0,1};
} }
class AI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI2ldb<dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern> string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern> { asm, "", pattern> {
let Inst{20} = 1; // L bit let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
@@ -262,9 +260,9 @@ class AI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
let Inst{27-26} = {0,1}; let Inst{27-26} = {0,1};
} }
class AXI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string asm, class AXI2ldb<dag oops, dag iops, Format f, string asm,
list<dag> pattern> list<dag> pattern>
: XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
asm, "", pattern> { asm, "", pattern> {
let Inst{20} = 1; // L bit let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
@@ -274,9 +272,9 @@ class AXI2ldb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
} }
// stores // stores
class AI2stw<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI2stw<dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern> string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern> { asm, "", pattern> {
let Inst{20} = 0; // L bit let Inst{20} = 0; // L bit
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
@@ -284,9 +282,9 @@ class AI2stw<bits<4> opcod, dag oops, dag iops, Format f, string opc,
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
let Inst{27-26} = {0,1}; let Inst{27-26} = {0,1};
} }
class AXI2stw<bits<4> opcod, dag oops, dag iops, Format f, string asm, class AXI2stw<dag oops, dag iops, Format f, string asm,
list<dag> pattern> list<dag> pattern>
: XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
asm, "", pattern> { asm, "", pattern> {
let Inst{20} = 0; // L bit let Inst{20} = 0; // L bit
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
@@ -294,9 +292,9 @@ class AXI2stw<bits<4> opcod, dag oops, dag iops, Format f, string asm,
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
let Inst{27-26} = {0,1}; let Inst{27-26} = {0,1};
} }
class AI2stb<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI2stb<dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern> string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc, : I<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern> { asm, "", pattern> {
let Inst{20} = 0; // L bit let Inst{20} = 0; // L bit
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
@@ -304,9 +302,9 @@ class AI2stb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
let Inst{27-26} = {0,1}; let Inst{27-26} = {0,1};
} }
class AXI2stb<bits<4> opcod, dag oops, dag iops, Format f, string asm, class AXI2stb<dag oops, dag iops, Format f, string asm,
list<dag> pattern> list<dag> pattern>
: XI<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f, : XI<oops, iops, AddrMode2, Size4Bytes, IndexModeNone, f,
asm, "", pattern> { asm, "", pattern> {
let Inst{20} = 0; // L bit let Inst{20} = 0; // L bit
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
@@ -316,9 +314,9 @@ class AXI2stb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
} }
// Pre-indexed loads // Pre-indexed loads
class AI2ldwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI2ldwpr<dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern> string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
asm, cstr, pattern> { asm, cstr, pattern> {
let Inst{20} = 1; // L bit let Inst{20} = 1; // L bit
let Inst{21} = 1; // W bit let Inst{21} = 1; // W bit
@@ -326,9 +324,9 @@ class AI2ldwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
let Inst{27-26} = {0,1}; let Inst{27-26} = {0,1};
} }
class AI2ldbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI2ldbpr<dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern> string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
asm, cstr, pattern> { asm, cstr, pattern> {
let Inst{20} = 1; // L bit let Inst{20} = 1; // L bit
let Inst{21} = 1; // W bit let Inst{21} = 1; // W bit
@@ -338,9 +336,9 @@ class AI2ldbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
} }
// Pre-indexed stores // Pre-indexed stores
class AI2stwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI2stwpr<dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern> string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
asm, cstr, pattern> { asm, cstr, pattern> {
let Inst{20} = 0; // L bit let Inst{20} = 0; // L bit
let Inst{21} = 1; // W bit let Inst{21} = 1; // W bit
@@ -348,9 +346,9 @@ class AI2stwpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
let Inst{27-26} = {0,1}; let Inst{27-26} = {0,1};
} }
class AI2stbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI2stbpr<dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern> string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc, : I<oops, iops, AddrMode2, Size4Bytes, IndexModePre, f, opc,
asm, cstr, pattern> { asm, cstr, pattern> {
let Inst{20} = 0; // L bit let Inst{20} = 0; // L bit
let Inst{21} = 1; // W bit let Inst{21} = 1; // W bit
@@ -360,9 +358,9 @@ class AI2stbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
} }
// Post-indexed loads // Post-indexed loads
class AI2ldwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI2ldwpo<dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern> string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
asm, cstr,pattern> { asm, cstr,pattern> {
let Inst{20} = 1; // L bit let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
@@ -370,9 +368,9 @@ class AI2ldwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
let Inst{24} = 0; // P bit let Inst{24} = 0; // P bit
let Inst{27-26} = {0,1}; let Inst{27-26} = {0,1};
} }
class AI2ldbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI2ldbpo<dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern> string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
asm, cstr,pattern> { asm, cstr,pattern> {
let Inst{20} = 1; // L bit let Inst{20} = 1; // L bit
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
@@ -382,9 +380,9 @@ class AI2ldbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
} }
// Post-indexed stores // Post-indexed stores
class AI2stwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI2stwpo<dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern> string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
asm, cstr,pattern> { asm, cstr,pattern> {
let Inst{20} = 0; // L bit let Inst{20} = 0; // L bit
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
@@ -392,9 +390,9 @@ class AI2stwpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
let Inst{24} = 0; // P bit let Inst{24} = 0; // P bit
let Inst{27-26} = {0,1}; let Inst{27-26} = {0,1};
} }
class AI2stbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI2stbpo<dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern> string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc, : I<oops, iops, AddrMode2, Size4Bytes, IndexModePost, f, opc,
asm, cstr,pattern> { asm, cstr,pattern> {
let Inst{20} = 0; // L bit let Inst{20} = 0; // L bit
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
@@ -404,19 +402,19 @@ class AI2stbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
} }
// addrmode3 instructions // addrmode3 instructions
class AI3<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI3<dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern> string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern>; asm, "", pattern>;
class AXI3<bits<4> opcod, dag oops, dag iops, Format f, string asm, class AXI3<dag oops, dag iops, Format f, string asm,
list<dag> pattern> list<dag> pattern>
: XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm, : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, asm,
"", pattern>; "", pattern>;
// loads // loads
class AI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI3ldh<dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern> string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern> { asm, "", pattern> {
let Inst{4} = 1; let Inst{4} = 1;
let Inst{5} = 1; // H bit let Inst{5} = 1; // H bit
@@ -426,9 +424,9 @@ class AI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
} }
class AXI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string asm, class AXI3ldh<dag oops, dag iops, Format f, string asm,
list<dag> pattern> list<dag> pattern>
: XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
asm, "", pattern> { asm, "", pattern> {
let Inst{4} = 1; let Inst{4} = 1;
let Inst{5} = 1; // H bit let Inst{5} = 1; // H bit
@@ -438,9 +436,9 @@ class AXI3ldh<bits<4> opcod, dag oops, dag iops, Format f, string asm,
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
} }
class AI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI3ldsh<dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern> string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern> { asm, "", pattern> {
let Inst{4} = 1; let Inst{4} = 1;
let Inst{5} = 1; // H bit let Inst{5} = 1; // H bit
@@ -450,9 +448,9 @@ class AI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string opc,
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
} }
class AXI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string asm, class AXI3ldsh<dag oops, dag iops, Format f, string asm,
list<dag> pattern> list<dag> pattern>
: XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
asm, "", pattern> { asm, "", pattern> {
let Inst{4} = 1; let Inst{4} = 1;
let Inst{5} = 1; // H bit let Inst{5} = 1; // H bit
@@ -462,9 +460,9 @@ class AXI3ldsh<bits<4> opcod, dag oops, dag iops, Format f, string asm,
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
} }
class AI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI3ldsb<dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern> string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern> { asm, "", pattern> {
let Inst{4} = 1; let Inst{4} = 1;
let Inst{5} = 0; // H bit let Inst{5} = 0; // H bit
@@ -474,9 +472,9 @@ class AI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string opc,
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
} }
class AXI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string asm, class AXI3ldsb<dag oops, dag iops, Format f, string asm,
list<dag> pattern> list<dag> pattern>
: XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
asm, "", pattern> { asm, "", pattern> {
let Inst{4} = 1; let Inst{4} = 1;
let Inst{5} = 0; // H bit let Inst{5} = 0; // H bit
@@ -486,9 +484,9 @@ class AXI3ldsb<bits<4> opcod, dag oops, dag iops, Format f, string asm,
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
} }
class AI3ldd<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI3ldd<dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern> string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern> { asm, "", pattern> {
let Inst{4} = 1; let Inst{4} = 1;
let Inst{5} = 0; // H bit let Inst{5} = 0; // H bit
@@ -500,9 +498,9 @@ class AI3ldd<bits<4> opcod, dag oops, dag iops, Format f, string opc,
} }
// stores // stores
class AI3sth<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI3sth<dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern> string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern> { asm, "", pattern> {
let Inst{4} = 1; let Inst{4} = 1;
let Inst{5} = 1; // H bit let Inst{5} = 1; // H bit
@@ -512,9 +510,9 @@ class AI3sth<bits<4> opcod, dag oops, dag iops, Format f, string opc,
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
} }
class AXI3sth<bits<4> opcod, dag oops, dag iops, Format f, string asm, class AXI3sth<dag oops, dag iops, Format f, string asm,
list<dag> pattern> list<dag> pattern>
: XI<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, : XI<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f,
asm, "", pattern> { asm, "", pattern> {
let Inst{4} = 1; let Inst{4} = 1;
let Inst{5} = 1; // H bit let Inst{5} = 1; // H bit
@@ -524,9 +522,9 @@ class AXI3sth<bits<4> opcod, dag oops, dag iops, Format f, string asm,
let Inst{21} = 0; // W bit let Inst{21} = 0; // W bit
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
} }
class AI3std<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI3std<dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern> string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc, : I<oops, iops, AddrMode3, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern> { asm, "", pattern> {
let Inst{4} = 1; let Inst{4} = 1;
let Inst{5} = 1; // H bit let Inst{5} = 1; // H bit
@@ -538,9 +536,9 @@ class AI3std<bits<4> opcod, dag oops, dag iops, Format f, string opc,
} }
// Pre-indexed loads // Pre-indexed loads
class AI3ldhpr<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI3ldhpr<dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern> string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
asm, cstr, pattern> { asm, cstr, pattern> {
let Inst{4} = 1; let Inst{4} = 1;
let Inst{5} = 1; // H bit let Inst{5} = 1; // H bit
@@ -550,9 +548,9 @@ class AI3ldhpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
let Inst{21} = 1; // W bit let Inst{21} = 1; // W bit
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
} }
class AI3ldshpr<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI3ldshpr<dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern> string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
asm, cstr, pattern> { asm, cstr, pattern> {
let Inst{4} = 1; let Inst{4} = 1;
let Inst{5} = 1; // H bit let Inst{5} = 1; // H bit
@@ -562,9 +560,9 @@ class AI3ldshpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
let Inst{21} = 1; // W bit let Inst{21} = 1; // W bit
let Inst{24} = 1; // P bit let Inst{24} = 1; // P bit
} }
class AI3ldsbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI3ldsbpr<dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern> string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
asm, cstr, pattern> { asm, cstr, pattern> {
let Inst{4} = 1; let Inst{4} = 1;
let Inst{5} = 0; // H bit let Inst{5} = 0; // H bit
@@ -576,9 +574,9 @@ class AI3ldsbpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
} }
// Pre-indexed stores // Pre-indexed stores
class AI3sthpr<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI3sthpr<dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern> string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc, : I<oops, iops, AddrMode3, Size4Bytes, IndexModePre, f, opc,
asm, cstr, pattern> { asm, cstr, pattern> {
let Inst{4} = 1; let Inst{4} = 1;
let Inst{5} = 1; // H bit let Inst{5} = 1; // H bit
@@ -590,9 +588,9 @@ class AI3sthpr<bits<4> opcod, dag oops, dag iops, Format f, string opc,
} }
// Post-indexed loads // Post-indexed loads
class AI3ldhpo<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI3ldhpo<dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern> string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
asm, cstr,pattern> { asm, cstr,pattern> {
let Inst{4} = 1; let Inst{4} = 1;
let Inst{5} = 1; // H bit let Inst{5} = 1; // H bit
@@ -602,9 +600,9 @@ class AI3ldhpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
let Inst{21} = 1; // W bit let Inst{21} = 1; // W bit
let Inst{24} = 0; // P bit let Inst{24} = 0; // P bit
} }
class AI3ldshpo<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI3ldshpo<dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern> string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
asm, cstr,pattern> { asm, cstr,pattern> {
let Inst{4} = 1; let Inst{4} = 1;
let Inst{5} = 1; // H bit let Inst{5} = 1; // H bit
@@ -614,9 +612,9 @@ class AI3ldshpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
let Inst{21} = 1; // W bit let Inst{21} = 1; // W bit
let Inst{24} = 0; // P bit let Inst{24} = 0; // P bit
} }
class AI3ldsbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI3ldsbpo<dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern> string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
asm, cstr,pattern> { asm, cstr,pattern> {
let Inst{4} = 1; let Inst{4} = 1;
let Inst{5} = 0; // H bit let Inst{5} = 0; // H bit
@@ -628,9 +626,9 @@ class AI3ldsbpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
} }
// Post-indexed stores // Post-indexed stores
class AI3sthpo<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI3sthpo<dag oops, dag iops, Format f, string opc,
string asm, string cstr, list<dag> pattern> string asm, string cstr, list<dag> pattern>
: I<opcod, oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc, : I<oops, iops, AddrMode3, Size4Bytes, IndexModePost, f, opc,
asm, cstr,pattern> { asm, cstr,pattern> {
let Inst{4} = 1; let Inst{4} = 1;
let Inst{5} = 1; // H bit let Inst{5} = 1; // H bit
@@ -643,30 +641,30 @@ class AI3sthpo<bits<4> opcod, dag oops, dag iops, Format f, string opc,
// addrmode4 instructions // addrmode4 instructions
class AI4<bits<4> opcod, dag oops, dag iops, Format f, string opc, class AI4<dag oops, dag iops, Format f, string opc,
string asm, list<dag> pattern> string asm, list<dag> pattern>
: I<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc, : I<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, opc,
asm, "", pattern> { asm, "", pattern> {
let Inst{25-27} = {0,0,1}; let Inst{25-27} = {0,0,1};
} }
class AXI4ld<bits<4> opcod, dag oops, dag iops, Format f, string asm, class AXI4ld<dag oops, dag iops, Format f, string asm,
list<dag> pattern> list<dag> pattern>
: XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm, : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
"", pattern> { "", pattern> {
let Inst{20} = 1; // L bit let Inst{20} = 1; // L bit
let Inst{22} = 0; // S bit let Inst{22} = 0; // S bit
let Inst{27-25} = 0b100; let Inst{27-25} = 0b100;
} }
class AXI4ldpc<bits<4> opcod, dag oops, dag iops, Format f, string asm, class AXI4ldpc<dag oops, dag iops, Format f, string asm,
list<dag> pattern> list<dag> pattern>
: XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm, : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
"", pattern> { "", pattern> {
let Inst{20} = 1; // L bit let Inst{20} = 1; // L bit
let Inst{27-25} = 0b100; let Inst{27-25} = 0b100;
} }
class AXI4st<bits<4> opcod, dag oops, dag iops, Format f, string asm, class AXI4st<dag oops, dag iops, Format f, string asm,
list<dag> pattern> list<dag> pattern>
: XI<opcod, oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm, : XI<oops, iops, AddrMode4, Size4Bytes, IndexModeNone, f, asm,
"", pattern> { "", pattern> {
let Inst{20} = 0; // L bit let Inst{20} = 0; // L bit
let Inst{22} = 0; // S bit let Inst{22} = 0; // S bit
@@ -674,41 +672,41 @@ class AXI4st<bits<4> opcod, dag oops, dag iops, Format f, string asm,
} }
// Unsigned multiply, multiply-accumulate instructions. // Unsigned multiply, multiply-accumulate instructions.
class AMul1I<bits<7> mulopc, dag oops, dag iops, string opc, class AMul1I<bits<7> opcod, dag oops, dag iops, string opc,
string asm, list<dag> pattern> string asm, list<dag> pattern>
: I<0, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
asm,"",pattern> { asm,"",pattern> {
let Inst{7-4} = 0b1001; let Inst{7-4} = 0b1001;
let Inst{20} = 0; // S bit let Inst{20} = 0; // S bit
let Inst{27-21} = mulopc; let Inst{27-21} = opcod;
} }
class AsMul1I<bits<7> mulopc, dag oops, dag iops, string opc, class AsMul1I<bits<7> opcod, dag oops, dag iops, string opc,
string asm, list<dag> pattern> string asm, list<dag> pattern>
: sI<0, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, : sI<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
asm,"",pattern> { asm,"",pattern> {
let Inst{7-4} = 0b1001; let Inst{7-4} = 0b1001;
let Inst{27-21} = mulopc; let Inst{27-21} = opcod;
} }
// Most significant word multiply // Most significant word multiply
class AMul2I<bits<7> mulopc, dag oops, dag iops, string opc, class AMul2I<bits<7> opcod, dag oops, dag iops, string opc,
string asm, list<dag> pattern> string asm, list<dag> pattern>
: I<0, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
asm,"",pattern> { asm,"",pattern> {
let Inst{7-4} = 0b1001; let Inst{7-4} = 0b1001;
let Inst{20} = 1; let Inst{20} = 1;
let Inst{27-21} = mulopc; let Inst{27-21} = opcod;
} }
// SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y> // SMUL<x><y> / SMULW<y> / SMLA<x><y> / SMLAW<x><y>
class AMulxyI<bits<7> mulopc, dag oops, dag iops, string opc, class AMulxyI<bits<7> opcod, dag oops, dag iops, string opc,
string asm, list<dag> pattern> string asm, list<dag> pattern>
: I<0, oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc, : I<oops, iops, AddrModeNone, Size4Bytes, IndexModeNone, MulFrm, opc,
asm,"",pattern> { asm,"",pattern> {
let Inst{4} = 0; let Inst{4} = 0;
let Inst{7} = 1; let Inst{7} = 1;
let Inst{20} = 0; let Inst{20} = 0;
let Inst{27-21} = mulopc; let Inst{27-21} = opcod;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@@ -734,8 +732,7 @@ class ARMV6Pat<dag pattern, dag result> : Pat<pattern, result> {
class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz, class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
string asm, string cstr, list<dag> pattern> string asm, string cstr, list<dag> pattern>
// FIXME: Set all opcodes to 0 for now. : InstARM<am, sz, IndexModeNone, ThumbFrm, cstr> {
: InstARM<0, am, sz, IndexModeNone, ThumbFrm, cstr> {
let OutOperandList = outs; let OutOperandList = outs;
let InOperandList = ins; let InOperandList = ins;
let AsmString = asm; let AsmString = asm;

8
lib/Target/ARM/ARMInstrInfo.h
View File

@@ -59,21 +59,17 @@ namespace ARMII {
IndexModePre = 1, IndexModePre = 1,
IndexModePost = 2, IndexModePost = 2,
// Opcode
OpcodeShift = 9,
OpcodeMask = 0xf << OpcodeShift,
//===------------------------------------------------------------------===// //===------------------------------------------------------------------===//
// Misc flags. // Misc flags.
// UnaryDP - Indicates this is a unary data processing instruction, i.e. // UnaryDP - Indicates this is a unary data processing instruction, i.e.
// it doesn't have a Rn operand. // it doesn't have a Rn operand.
UnaryDP = 1 << 13, UnaryDP = 1 << 9,
//===------------------------------------------------------------------===// //===------------------------------------------------------------------===//
// Instruction encoding formats. // Instruction encoding formats.
// //
FormShift = 14, FormShift = 10,
FormMask = 0xf << FormShift, FormMask = 0xf << FormShift,
// Pseudo instructions // Pseudo instructions

167
lib/Target/ARM/ARMInstrInfo.td
View File

@@ -390,11 +390,11 @@ multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
/// AI_unary_rrot - A unary operation with two forms: one whose operand is a /// AI_unary_rrot - A unary operation with two forms: one whose operand is a
/// register and one whose operand is a register rotated by 8/16/24. /// register and one whose operand is a register rotated by 8/16/24.
multiclass AI_unary_rrot<bits<4> opcod, string opc, PatFrag opnode> { multiclass AI_unary_rrot<string opc, PatFrag opnode> {
def r : AI<opcod, (outs GPR:$dst), (ins GPR:$Src), Pseudo, def r : AI<(outs GPR:$dst), (ins GPR:$Src), Pseudo,
opc, " $dst, $Src", opc, " $dst, $Src",
[(set GPR:$dst, (opnode GPR:$Src))]>, Requires<[IsARM, HasV6]>; [(set GPR:$dst, (opnode GPR:$Src))]>, Requires<[IsARM, HasV6]>;
def r_rot : AI<opcod, (outs GPR:$dst), (ins GPR:$Src, i32imm:$rot), Pseudo, def r_rot : AI<(outs GPR:$dst), (ins GPR:$Src, i32imm:$rot), Pseudo,
opc, " $dst, $Src, ror $rot", opc, " $dst, $Src, ror $rot",
[(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>, [(set GPR:$dst, (opnode (rotr GPR:$Src, rot_imm:$rot)))]>,
Requires<[IsARM, HasV6]>; Requires<[IsARM, HasV6]>;
@@ -402,12 +402,12 @@ multiclass AI_unary_rrot<bits<4> opcod, string opc, PatFrag opnode> {
/// AI_bin_rrot - A binary operation with two forms: one whose operand is a /// AI_bin_rrot - A binary operation with two forms: one whose operand is a
/// register and one whose operand is a register rotated by 8/16/24. /// register and one whose operand is a register rotated by 8/16/24.
multiclass AI_bin_rrot<bits<4> opcod, string opc, PatFrag opnode> { multiclass AI_bin_rrot<string opc, PatFrag opnode> {
def rr : AI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS), def rr : AI<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS),
Pseudo, opc, " $dst, $LHS, $RHS", Pseudo, opc, " $dst, $LHS, $RHS",
[(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>, [(set GPR:$dst, (opnode GPR:$LHS, GPR:$RHS))]>,
Requires<[IsARM, HasV6]>; Requires<[IsARM, HasV6]>;
def rr_rot : AI<opcod, (outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot), def rr_rot : AI<(outs GPR:$dst), (ins GPR:$LHS, GPR:$RHS, i32imm:$rot),
Pseudo, opc, " $dst, $LHS, $RHS, ror $rot", Pseudo, opc, " $dst, $LHS, $RHS, ror $rot",
[(set GPR:$dst, (opnode GPR:$LHS, [(set GPR:$dst, (opnode GPR:$LHS,
(rotr GPR:$RHS, rot_imm:$rot)))]>, (rotr GPR:$RHS, rot_imm:$rot)))]>,
@@ -472,36 +472,36 @@ def PICADD : AXI1<0b0100, (outs GPR:$dst), (ins GPR:$a, pclabel:$cp, pred:$p),
let AddedComplexity = 10 in { let AddedComplexity = 10 in {
let isSimpleLoad = 1 in let isSimpleLoad = 1 in
def PICLDR : AXI2ldw<0x0, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), def PICLDR : AXI2ldw<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, "${addr:label}:\n\tldr$p $dst, $addr", Pseudo, "${addr:label}:\n\tldr$p $dst, $addr",
[(set GPR:$dst, (load addrmodepc:$addr))]>; [(set GPR:$dst, (load addrmodepc:$addr))]>;
def PICLDRH : AXI3ldh<0xB, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), def PICLDRH : AXI3ldh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr", Pseudo, "${addr:label}:\n\tldr${p}h $dst, $addr",
[(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>; [(set GPR:$dst, (zextloadi16 addrmodepc:$addr))]>;
def PICLDRB : AXI2ldb<0x1, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), def PICLDRB : AXI2ldb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr", Pseudo, "${addr:label}:\n\tldr${p}b $dst, $addr",
[(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>; [(set GPR:$dst, (zextloadi8 addrmodepc:$addr))]>;
def PICLDRSH : AXI3ldsh<0xE, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), def PICLDRSH : AXI3ldsh<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, "${addr:label}:\n\tldr${p}sh $dst, $addr", Pseudo, "${addr:label}:\n\tldr${p}sh $dst, $addr",
[(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>; [(set GPR:$dst, (sextloadi16 addrmodepc:$addr))]>;
def PICLDRSB : AXI3ldsb<0xD, (outs GPR:$dst), (ins addrmodepc:$addr, pred:$p), def PICLDRSB : AXI3ldsb<(outs GPR:$dst), (ins addrmodepc:$addr, pred:$p),
Pseudo, "${addr:label}:\n\tldr${p}sb $dst, $addr", Pseudo, "${addr:label}:\n\tldr${p}sb $dst, $addr",
[(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>; [(set GPR:$dst, (sextloadi8 addrmodepc:$addr))]>;
} }
let AddedComplexity = 10 in { let AddedComplexity = 10 in {
def PICSTR : AXI2stw<0x0, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), def PICSTR : AXI2stw<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
Pseudo, "${addr:label}:\n\tstr$p $src, $addr", Pseudo, "${addr:label}:\n\tstr$p $src, $addr",
[(store GPR:$src, addrmodepc:$addr)]>; [(store GPR:$src, addrmodepc:$addr)]>;
def PICSTRH : AXI3sth<0xB, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), def PICSTRH : AXI3sth<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
Pseudo, "${addr:label}:\n\tstr${p}h $src, $addr", Pseudo, "${addr:label}:\n\tstr${p}h $src, $addr",
[(truncstorei16 GPR:$src, addrmodepc:$addr)]>; [(truncstorei16 GPR:$src, addrmodepc:$addr)]>;
def PICSTRB : AXI2stb<0x1, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p), def PICSTRB : AXI2stb<(outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
Pseudo, "${addr:label}:\n\tstr${p}b $src, $addr", Pseudo, "${addr:label}:\n\tstr${p}b $src, $addr",
[(truncstorei8 GPR:$src, addrmodepc:$addr)]>; [(truncstorei8 GPR:$src, addrmodepc:$addr)]>;
} }
@@ -512,7 +512,7 @@ def PICSTRB : AXI2stb<0x1, (outs), (ins GPR:$src, addrmodepc:$addr, pred:$p),
// //
let isReturn = 1, isTerminator = 1 in let isReturn = 1, isTerminator = 1 in
def BX_RET : AI<0x0, (outs), (ins), BranchMisc, "bx", " lr", [(ARMretflag)]> { def BX_RET : AI<(outs), (ins), BranchMisc, "bx", " lr", [(ARMretflag)]> {
let Inst{7-4} = 0b0001; let Inst{7-4} = 0b0001;
let Inst{19-8} = 0b111111111111; let Inst{19-8} = 0b111111111111;
let Inst{27-20} = 0b00010010; let Inst{27-20} = 0b00010010;
@@ -522,7 +522,7 @@ let isReturn = 1, isTerminator = 1 in
// FIXME: $dst1 should be a def. But the extra ops must be in the end of the // FIXME: $dst1 should be a def. But the extra ops must be in the end of the
// operand list. // operand list.
let isReturn = 1, isTerminator = 1 in let isReturn = 1, isTerminator = 1 in
def LDM_RET : AXI4ldpc<0x0, (outs), def LDM_RET : AXI4ldpc<(outs),
(ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
LdMulFrm, "ldm${p}${addr:submode} $addr, $dst1", LdMulFrm, "ldm${p}${addr:submode} $addr, $dst1",
[]>; []>;
@@ -530,16 +530,16 @@ let isReturn = 1, isTerminator = 1 in
let isCall = 1, let isCall = 1,
Defs = [R0, R1, R2, R3, R12, LR, Defs = [R0, R1, R2, R3, R12, LR,
D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in { D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
def BL : ABLI<0xB, (outs), (ins i32imm:$func, variable_ops), Branch, def BL : ABLI<0b1011, (outs), (ins i32imm:$func, variable_ops), Branch,
"bl ${func:call}", "bl ${func:call}",
[(ARMcall tglobaladdr:$func)]>; [(ARMcall tglobaladdr:$func)]>;
def BL_pred : ABLpredI<0xB, (outs), (ins i32imm:$func, variable_ops), Branch, def BL_pred : ABLpredI<0b1011, (outs), (ins i32imm:$func, variable_ops), Branch,
"bl", " ${func:call}", "bl", " ${func:call}",
[(ARMcall_pred tglobaladdr:$func)]>; [(ARMcall_pred tglobaladdr:$func)]>;
// ARMv5T and above // ARMv5T and above
def BLX : AXI<0x0, (outs), (ins GPR:$func, variable_ops), BranchMisc, def BLX : AXI<(outs), (ins GPR:$func, variable_ops), BranchMisc,
"blx $func", "blx $func",
[(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T]> { [(ARMcall GPR:$func)]>, Requires<[IsARM, HasV5T]> {
let Inst{7-4} = 0b0011; let Inst{7-4} = 0b0011;
@@ -549,7 +549,7 @@ let isCall = 1,
let Uses = [LR] in { let Uses = [LR] in {
// ARMv4T // ARMv4T
def BX : AXIx2<0x0, (outs), (ins GPR:$func, variable_ops), def BX : AXIx2<(outs), (ins GPR:$func, variable_ops),
BranchMisc, "mov lr, pc\n\tbx $func", BranchMisc, "mov lr, pc\n\tbx $func",
[(ARMcall_nolink GPR:$func)]>; [(ARMcall_nolink GPR:$func)]>;
} }
@@ -559,28 +559,31 @@ let isBranch = 1, isTerminator = 1 in {
// B is "predicable" since it can be xformed into a Bcc. // B is "predicable" since it can be xformed into a Bcc.
let isBarrier = 1 in { let isBarrier = 1 in {
let isPredicable = 1 in let isPredicable = 1 in
def B : ABI<0xA, (outs), (ins brtarget:$target), Branch, "b $target", def B : ABI<0b1010, (outs), (ins brtarget:$target), Branch, "b $target",
[(br bb:$target)]>; [(br bb:$target)]>;
let isNotDuplicable = 1, isIndirectBranch = 1 in { let isNotDuplicable = 1, isIndirectBranch = 1 in {
def BR_JTr : JTI<0b1101, (outs), (ins GPR:$target, jtblock_operand:$jt, i32imm:$id), def BR_JTr : JTI<0b1101, (outs),
(ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
"mov pc, $target \n$jt", "mov pc, $target \n$jt",
[(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>; [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
def BR_JTm : JTI2<0x0, (outs), (ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id), def BR_JTm : JTI2<0, (outs),
(ins addrmode2:$target, jtblock_operand:$jt, i32imm:$id),
"ldr pc, $target \n$jt", "ldr pc, $target \n$jt",
[(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt, [(ARMbrjt (i32 (load addrmode2:$target)), tjumptable:$jt,
imm:$id)]>; imm:$id)]>;
def BR_JTadd : JTI1<0b0100, (outs), (ins GPR:$target, GPR:$idx, jtblock_operand:$jt, def BR_JTadd : JTI1<0b0100, (outs),
i32imm:$id), (ins GPR:$target, GPR:$idx, jtblock_operand:$jt,
"add pc, $target, $idx \n$jt", i32imm:$id),
[(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt, "add pc, $target, $idx \n$jt",
imm:$id)]>; [(ARMbrjt (add GPR:$target, GPR:$idx), tjumptable:$jt,
imm:$id)]>;
} }
} }
// FIXME: should be able to write a pattern for ARMBrcond, but can't use // FIXME: should be able to write a pattern for ARMBrcond, but can't use
// a two-value operand where a dag node expects two operands. :( // a two-value operand where a dag node expects two operands. :(
def Bcc : ABccI<0xA, (outs), (ins brtarget:$target), Branch, def Bcc : ABccI<0b1010, (outs), (ins brtarget:$target), Branch,
"b", " $target", "b", " $target",
[/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>; [/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]>;
} }
@@ -591,133 +594,133 @@ let isBranch = 1, isTerminator = 1 in {
// Load // Load
let isSimpleLoad = 1 in let isSimpleLoad = 1 in
def LDR : AI2ldw<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm, def LDR : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
"ldr", " $dst, $addr", "ldr", " $dst, $addr",
[(set GPR:$dst, (load addrmode2:$addr))]>; [(set GPR:$dst, (load addrmode2:$addr))]>;
// Special LDR for loads from non-pc-relative constpools. // Special LDR for loads from non-pc-relative constpools.
let isSimpleLoad = 1, mayLoad = 1, isReMaterializable = 1 in let isSimpleLoad = 1, mayLoad = 1, isReMaterializable = 1 in
def LDRcp : AI2ldw<0x0, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm, def LDRcp : AI2ldw<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
"ldr", " $dst, $addr", []>; "ldr", " $dst, $addr", []>;
// Loads with zero extension // Loads with zero extension
def LDRH : AI3ldh<0xB, (outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, def LDRH : AI3ldh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
"ldr", "h $dst, $addr", "ldr", "h $dst, $addr",
[(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>; [(set GPR:$dst, (zextloadi16 addrmode3:$addr))]>;
def LDRB : AI2ldb<0x1, (outs GPR:$dst), (ins addrmode2:$addr), LdFrm, def LDRB : AI2ldb<(outs GPR:$dst), (ins addrmode2:$addr), LdFrm,
"ldr", "b $dst, $addr", "ldr", "b $dst, $addr",
[(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>; [(set GPR:$dst, (zextloadi8 addrmode2:$addr))]>;
// Loads with sign extension // Loads with sign extension
def LDRSH : AI3ldsh<0xE, (outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, def LDRSH : AI3ldsh<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
"ldr", "sh $dst, $addr", "ldr", "sh $dst, $addr",
[(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>; [(set GPR:$dst, (sextloadi16 addrmode3:$addr))]>;
def LDRSB : AI3ldsb<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, def LDRSB : AI3ldsb<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
"ldr", "sb $dst, $addr", "ldr", "sb $dst, $addr",
[(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>; [(set GPR:$dst, (sextloadi8 addrmode3:$addr))]>;
let mayLoad = 1 in { let mayLoad = 1 in {
// Load doubleword // Load doubleword
def LDRD : AI3ldd<0xD, (outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm, def LDRD : AI3ldd<(outs GPR:$dst), (ins addrmode3:$addr), LdMiscFrm,
"ldr", "d $dst, $addr", "ldr", "d $dst, $addr",
[]>, Requires<[IsARM, HasV5T]>; []>, Requires<[IsARM, HasV5T]>;
// Indexed loads // Indexed loads
def LDR_PRE : AI2ldwpr<0x0, (outs GPR:$dst, GPR:$base_wb), def LDR_PRE : AI2ldwpr<(outs GPR:$dst, GPR:$base_wb),
(ins addrmode2:$addr), LdFrm, (ins addrmode2:$addr), LdFrm,
"ldr", " $dst, $addr!", "$addr.base = $base_wb", []>; "ldr", " $dst, $addr!", "$addr.base = $base_wb", []>;
def LDR_POST : AI2ldwpo<0x0, (outs GPR:$dst, GPR:$base_wb), def LDR_POST : AI2ldwpo<(outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base, am2offset:$offset), LdFrm, (ins GPR:$base, am2offset:$offset), LdFrm,
"ldr", " $dst, [$base], $offset", "$base = $base_wb", []>; "ldr", " $dst, [$base], $offset", "$base = $base_wb", []>;
def LDRH_PRE : AI3ldhpr<0xB, (outs GPR:$dst, GPR:$base_wb), def LDRH_PRE : AI3ldhpr<(outs GPR:$dst, GPR:$base_wb),
(ins addrmode3:$addr), LdMiscFrm, (ins addrmode3:$addr), LdMiscFrm,
"ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>; "ldr", "h $dst, $addr!", "$addr.base = $base_wb", []>;
def LDRH_POST : AI3ldhpo<0xB, (outs GPR:$dst, GPR:$base_wb), def LDRH_POST : AI3ldhpo<(outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base,am3offset:$offset), LdMiscFrm, (ins GPR:$base,am3offset:$offset), LdMiscFrm,
"ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>; "ldr", "h $dst, [$base], $offset", "$base = $base_wb", []>;
def LDRB_PRE : AI2ldbpr<0x1, (outs GPR:$dst, GPR:$base_wb), def LDRB_PRE : AI2ldbpr<(outs GPR:$dst, GPR:$base_wb),
(ins addrmode2:$addr), LdFrm, (ins addrmode2:$addr), LdFrm,
"ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>; "ldr", "b $dst, $addr!", "$addr.base = $base_wb", []>;
def LDRB_POST : AI2ldbpo<0x1, (outs GPR:$dst, GPR:$base_wb), def LDRB_POST : AI2ldbpo<(outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base,am2offset:$offset), LdFrm, (ins GPR:$base,am2offset:$offset), LdFrm,
"ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>; "ldr", "b $dst, [$base], $offset", "$base = $base_wb", []>;
def LDRSH_PRE : AI3ldshpr<0xE, (outs GPR:$dst, GPR:$base_wb), def LDRSH_PRE : AI3ldshpr<(outs GPR:$dst, GPR:$base_wb),
(ins addrmode3:$addr), LdMiscFrm, (ins addrmode3:$addr), LdMiscFrm,
"ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>; "ldr", "sh $dst, $addr!", "$addr.base = $base_wb", []>;
def LDRSH_POST: AI3ldshpo<0xE, (outs GPR:$dst, GPR:$base_wb), def LDRSH_POST: AI3ldshpo<(outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base,am3offset:$offset), LdMiscFrm, (ins GPR:$base,am3offset:$offset), LdMiscFrm,
"ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>; "ldr", "sh $dst, [$base], $offset", "$base = $base_wb", []>;
def LDRSB_PRE : AI3ldsbpr<0xD, (outs GPR:$dst, GPR:$base_wb), def LDRSB_PRE : AI3ldsbpr<(outs GPR:$dst, GPR:$base_wb),
(ins addrmode3:$addr), LdMiscFrm, (ins addrmode3:$addr), LdMiscFrm,
"ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>; "ldr", "sb $dst, $addr!", "$addr.base = $base_wb", []>;
def LDRSB_POST: AI3ldsbpo<0xD, (outs GPR:$dst, GPR:$base_wb), def LDRSB_POST: AI3ldsbpo<(outs GPR:$dst, GPR:$base_wb),
(ins GPR:$base,am3offset:$offset), LdMiscFrm, (ins GPR:$base,am3offset:$offset), LdMiscFrm,
"ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>; "ldr", "sb $dst, [$base], $offset", "$base = $base_wb", []>;
} }
// Store // Store
def STR : AI2stw<0x0, (outs), (ins GPR:$src, addrmode2:$addr), StFrm, def STR : AI2stw<(outs), (ins GPR:$src, addrmode2:$addr), StFrm,
"str", " $src, $addr", "str", " $src, $addr",
[(store GPR:$src, addrmode2:$addr)]>; [(store GPR:$src, addrmode2:$addr)]>;
// Stores with truncate // Stores with truncate
def STRH : AI3sth<0xB, (outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, def STRH : AI3sth<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
"str", "h $src, $addr", "str", "h $src, $addr",
[(truncstorei16 GPR:$src, addrmode3:$addr)]>; [(truncstorei16 GPR:$src, addrmode3:$addr)]>;
def STRB : AI2stb<0x1, (outs), (ins GPR:$src, addrmode2:$addr), StFrm, def STRB : AI2stb<(outs), (ins GPR:$src, addrmode2:$addr), StFrm,
"str", "b $src, $addr", "str", "b $src, $addr",
[(truncstorei8 GPR:$src, addrmode2:$addr)]>; [(truncstorei8 GPR:$src, addrmode2:$addr)]>;
// Store doubleword // Store doubleword
let mayStore = 1 in let mayStore = 1 in
def STRD : AI3std<0xF, (outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm, def STRD : AI3std<(outs), (ins GPR:$src, addrmode3:$addr), StMiscFrm,
"str", "d $src, $addr", "str", "d $src, $addr",
[]>, Requires<[IsARM, HasV5T]>; []>, Requires<[IsARM, HasV5T]>;
// Indexed stores // Indexed stores
def STR_PRE : AI2stwpr<0x0, (outs GPR:$base_wb), def STR_PRE : AI2stwpr<(outs GPR:$base_wb),
(ins GPR:$src, GPR:$base, am2offset:$offset), StFrm, (ins GPR:$src, GPR:$base, am2offset:$offset), StFrm,
"str", " $src, [$base, $offset]!", "$base = $base_wb", "str", " $src, [$base, $offset]!", "$base = $base_wb",
[(set GPR:$base_wb, [(set GPR:$base_wb,
(pre_store GPR:$src, GPR:$base, am2offset:$offset))]>; (pre_store GPR:$src, GPR:$base, am2offset:$offset))]>;
def STR_POST : AI2stwpo<0x0, (outs GPR:$base_wb), def STR_POST : AI2stwpo<(outs GPR:$base_wb),
(ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
"str", " $src, [$base], $offset", "$base = $base_wb", "str", " $src, [$base], $offset", "$base = $base_wb",
[(set GPR:$base_wb, [(set GPR:$base_wb,
(post_store GPR:$src, GPR:$base, am2offset:$offset))]>; (post_store GPR:$src, GPR:$base, am2offset:$offset))]>;
def STRH_PRE : AI3sthpr<0xB, (outs GPR:$base_wb), def STRH_PRE : AI3sthpr<(outs GPR:$base_wb),
(ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm, (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm,
"str", "h $src, [$base, $offset]!", "$base = $base_wb", "str", "h $src, [$base, $offset]!", "$base = $base_wb",
[(set GPR:$base_wb, [(set GPR:$base_wb,
(pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>; (pre_truncsti16 GPR:$src, GPR:$base,am3offset:$offset))]>;
def STRH_POST: AI3sthpo<0xB, (outs GPR:$base_wb), def STRH_POST: AI3sthpo<(outs GPR:$base_wb),
(ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm, (ins GPR:$src, GPR:$base,am3offset:$offset), StMiscFrm,
"str", "h $src, [$base], $offset", "$base = $base_wb", "str", "h $src, [$base], $offset", "$base = $base_wb",
[(set GPR:$base_wb, (post_truncsti16 GPR:$src, [(set GPR:$base_wb, (post_truncsti16 GPR:$src,
GPR:$base, am3offset:$offset))]>; GPR:$base, am3offset:$offset))]>;
def STRB_PRE : AI2stbpr<0x1, (outs GPR:$base_wb), def STRB_PRE : AI2stbpr<(outs GPR:$base_wb),
(ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
"str", "b $src, [$base, $offset]!", "$base = $base_wb", "str", "b $src, [$base, $offset]!", "$base = $base_wb",
[(set GPR:$base_wb, (pre_truncsti8 GPR:$src, [(set GPR:$base_wb, (pre_truncsti8 GPR:$src,
GPR:$base, am2offset:$offset))]>; GPR:$base, am2offset:$offset))]>;
def STRB_POST: AI2stbpo<0x1, (outs GPR:$base_wb), def STRB_POST: AI2stbpo<(outs GPR:$base_wb),
(ins GPR:$src, GPR:$base,am2offset:$offset), StFrm, (ins GPR:$src, GPR:$base,am2offset:$offset), StFrm,
"str", "b $src, [$base], $offset", "$base = $base_wb", "str", "b $src, [$base], $offset", "$base = $base_wb",
[(set GPR:$base_wb, (post_truncsti8 GPR:$src, [(set GPR:$base_wb, (post_truncsti8 GPR:$src,
@@ -729,13 +732,13 @@ def STRB_POST: AI2stbpo<0x1, (outs GPR:$base_wb),
// FIXME: $dst1 should be a def. // FIXME: $dst1 should be a def.
let mayLoad = 1 in let mayLoad = 1 in
def LDM : AXI4ld<0x0, (outs), def LDM : AXI4ld<(outs),
(ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops), (ins addrmode4:$addr, pred:$p, reglist:$dst1, variable_ops),
LdMulFrm, "ldm${p}${addr:submode} $addr, $dst1", LdMulFrm, "ldm${p}${addr:submode} $addr, $dst1",
[]>; []>;
let mayStore = 1 in let mayStore = 1 in
def STM : AXI4st<0x0, (outs), def STM : AXI4st<(outs),
(ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops), (ins addrmode4:$addr, pred:$p, reglist:$src1, variable_ops),
StMulFrm, "stm${p}${addr:submode} $addr, $src1", StMulFrm, "stm${p}${addr:submode} $addr, $src1",
[]>; []>;
@@ -775,12 +778,12 @@ def MOVsra_flag : AI1<0b1101, (outs GPR:$dst), (ins GPR:$src), DPFrm,
// Sign extenders // Sign extenders
defm SXTB : AI_unary_rrot<0x0, "sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>; defm SXTB : AI_unary_rrot<"sxtb", UnOpFrag<(sext_inreg node:$Src, i8)>>;
defm SXTH : AI_unary_rrot<0x0, "sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>; defm SXTH : AI_unary_rrot<"sxth", UnOpFrag<(sext_inreg node:$Src, i16)>>;
defm SXTAB : AI_bin_rrot<0x0, "sxtab", defm SXTAB : AI_bin_rrot<"sxtab",
BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>; BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS, i8))>>;
defm SXTAH : AI_bin_rrot<0x0, "sxtah", defm SXTAH : AI_bin_rrot<"sxtah",
BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>; BinOpFrag<(add node:$LHS, (sext_inreg node:$RHS,i16))>>;
// TODO: SXT(A){B|H}16 // TODO: SXT(A){B|H}16
@@ -788,18 +791,18 @@ defm SXTAH : AI_bin_rrot<0x0, "sxtah",
// Zero extenders // Zero extenders
let AddedComplexity = 16 in { let AddedComplexity = 16 in {
defm UXTB : AI_unary_rrot<0x0, "uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>; defm UXTB : AI_unary_rrot<"uxtb" , UnOpFrag<(and node:$Src, 0x000000FF)>>;
defm UXTH : AI_unary_rrot<0x0, "uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>; defm UXTH : AI_unary_rrot<"uxth" , UnOpFrag<(and node:$Src, 0x0000FFFF)>>;
defm UXTB16 : AI_unary_rrot<0x0, "uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>; defm UXTB16 : AI_unary_rrot<"uxtb16", UnOpFrag<(and node:$Src, 0x00FF00FF)>>;
def : ARMV6Pat<(and (shl GPR:$Src, 8), 0xFF00FF), def : ARMV6Pat<(and (shl GPR:$Src, 8), 0xFF00FF),
(UXTB16r_rot GPR:$Src, 24)>; (UXTB16r_rot GPR:$Src, 24)>;
def : ARMV6Pat<(and (srl GPR:$Src, 8), 0xFF00FF), def : ARMV6Pat<(and (srl GPR:$Src, 8), 0xFF00FF),
(UXTB16r_rot GPR:$Src, 8)>; (UXTB16r_rot GPR:$Src, 8)>;
defm UXTAB : AI_bin_rrot<0x0, "uxtab", defm UXTAB : AI_bin_rrot<"uxtab",
BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>; BinOpFrag<(add node:$LHS, (and node:$RHS, 0x00FF))>>;
defm UXTAH : AI_bin_rrot<0x0, "uxtah", defm UXTAH : AI_bin_rrot<"uxtah",
BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>; BinOpFrag<(add node:$LHS, (and node:$RHS, 0xFFFF))>>;
} }
@@ -1086,15 +1089,15 @@ defm SMLA : AI_smla<"smla", BinOpFrag<(mul node:$LHS, node:$RHS)>>;
// Misc. Arithmetic Instructions. // Misc. Arithmetic Instructions.
// //
def CLZ : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc, def CLZ : AI<(outs GPR:$dst), (ins GPR:$src), ArithMisc,
"clz", " $dst, $src", "clz", " $dst, $src",
[(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]>; [(set GPR:$dst, (ctlz GPR:$src))]>, Requires<[IsARM, HasV5T]>;
def REV : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc, def REV : AI<(outs GPR:$dst), (ins GPR:$src), ArithMisc,
"rev", " $dst, $src", "rev", " $dst, $src",
[(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]>; [(set GPR:$dst, (bswap GPR:$src))]>, Requires<[IsARM, HasV6]>;
def REV16 : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc, def REV16 : AI<(outs GPR:$dst), (ins GPR:$src), ArithMisc,
"rev16", " $dst, $src", "rev16", " $dst, $src",
[(set GPR:$dst, [(set GPR:$dst,
(or (and (srl GPR:$src, 8), 0xFF), (or (and (srl GPR:$src, 8), 0xFF),
@@ -1103,7 +1106,7 @@ def REV16 : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc,
(and (shl GPR:$src, 8), 0xFF000000)))))]>, (and (shl GPR:$src, 8), 0xFF000000)))))]>,
Requires<[IsARM, HasV6]>; Requires<[IsARM, HasV6]>;
def REVSH : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc, def REVSH : AI<(outs GPR:$dst), (ins GPR:$src), ArithMisc,
"revsh", " $dst, $src", "revsh", " $dst, $src",
[(set GPR:$dst, [(set GPR:$dst,
(sext_inreg (sext_inreg
@@ -1111,7 +1114,7 @@ def REVSH : AI<0x0, (outs GPR:$dst), (ins GPR:$src), ArithMisc,
(shl GPR:$src, 8)), i16))]>, (shl GPR:$src, 8)), i16))]>,
Requires<[IsARM, HasV6]>; Requires<[IsARM, HasV6]>;
def PKHBT : AI<0x0, (outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt), def PKHBT : AI<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
Pseudo, "pkhbt", " $dst, $src1, $src2, LSL $shamt", Pseudo, "pkhbt", " $dst, $src1, $src2, LSL $shamt",
[(set GPR:$dst, (or (and GPR:$src1, 0xFFFF), [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
(and (shl GPR:$src2, (i32 imm:$shamt)), (and (shl GPR:$src2, (i32 imm:$shamt)),
@@ -1125,7 +1128,7 @@ def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
(PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>; (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
def PKHTB : AI<0x0, (outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt), def PKHTB : AI<(outs GPR:$dst), (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
Pseudo, "pkhtb", " $dst, $src1, $src2, ASR $shamt", Pseudo, "pkhtb", " $dst, $src1, $src2, ASR $shamt",
[(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000), [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
(and (sra GPR:$src2, imm16_31:$shamt), (and (sra GPR:$src2, imm16_31:$shamt),
@@ -1150,9 +1153,9 @@ defm CMN : AI1_cmp_irs<0b1011, "cmn",
BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>; BinOpFrag<(ARMcmp node:$LHS,(ineg node:$RHS))>>;
// Note that TST/TEQ don't set all the same flags that CMP does! // Note that TST/TEQ don't set all the same flags that CMP does!
defm TST : AI1_cmp_irs<0x8, "tst", defm TST : AI1_cmp_irs<0b1000, "tst",
BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>; BinOpFrag<(ARMcmpNZ (and node:$LHS, node:$RHS), 0)>>;
defm TEQ : AI1_cmp_irs<0x9, "teq", defm TEQ : AI1_cmp_irs<0b1001, "teq",
BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>; BinOpFrag<(ARMcmpNZ (xor node:$LHS, node:$RHS), 0)>>;
defm CMPnz : AI1_cmp_irs<0b1010, "cmp", defm CMPnz : AI1_cmp_irs<0b1010, "cmp",
@@ -1170,17 +1173,19 @@ def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm),
// Conditional moves // Conditional moves
// FIXME: should be able to write a pattern for ARMcmov, but can't use // FIXME: should be able to write a pattern for ARMcmov, but can't use
// a two-value operand where a dag node expects two operands. :( // a two-value operand where a dag node expects two operands. :(
def MOVCCr : AI<0xD, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm, def MOVCCr : AI1<0b1101, (outs GPR:$dst), (ins GPR:$false, GPR:$true), DPFrm,
"mov", " $dst, $true", "mov", " $dst, $true",
[/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>, [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $dst">; RegConstraint<"$false = $dst">, UnaryDP;
def MOVCCs : AI<0xD, (outs GPR:$dst), (ins GPR:$false, so_reg:$true), DPSoRegFrm, def MOVCCs : AI1<0b1101, (outs GPR:$dst),
(ins GPR:$false, so_reg:$true), DPSoRegFrm,
"mov", " $dst, $true", "mov", " $dst, $true",
[/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>, [/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $dst">, UnaryDP; RegConstraint<"$false = $dst">, UnaryDP;
def MOVCCi : AI<0xD, (outs GPR:$dst), (ins GPR:$false, so_imm:$true), DPFrm, def MOVCCi : AI1<0b1101, (outs GPR:$dst),
(ins GPR:$false, so_imm:$true), DPFrm,
"mov", " $dst, $true", "mov", " $dst, $true",
[/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>, [/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $dst">, UnaryDP; RegConstraint<"$false = $dst">, UnaryDP;
@@ -1210,7 +1215,7 @@ def LEApcrelJT : AXI1<0x0, (outs GPR:$dst), (ins i32imm:$label, i32imm:$id, pred
// __aeabi_read_tp preserves the registers r1-r3. // __aeabi_read_tp preserves the registers r1-r3.
let isCall = 1, let isCall = 1,
Defs = [R0, R12, LR, CPSR] in { Defs = [R0, R12, LR, CPSR] in {
def TPsoft : AXI<0x0, (outs), (ins), BranchMisc, def TPsoft : AXI<(outs), (ins), BranchMisc,
"bl __aeabi_read_tp", "bl __aeabi_read_tp",
[(set R0, ARMthread_pointer)]>; [(set R0, ARMthread_pointer)]>;
} }
@@ -1229,7 +1234,7 @@ def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
// Two piece so_imms. // Two piece so_imms.
let isReMaterializable = 1 in let isReMaterializable = 1 in
def MOVi2pieces : AI1x2<0x0, (outs GPR:$dst), (ins so_imm2part:$src), Pseudo, def MOVi2pieces : AI1x2<(outs GPR:$dst), (ins so_imm2part:$src), Pseudo,
"mov", " $dst, $src", "mov", " $dst, $src",
[(set GPR:$dst, so_imm2part:$src)]>; [(set GPR:$dst, so_imm2part:$src)]>;

16
lib/Target/ARM/ARMInstrVFP.td
View File

@@ -17,49 +17,49 @@
// ARM Float Instruction // ARM Float Instruction
class ASI<dag outs, dag ins, string opc, string asm, list<dag> pattern> class ASI<dag outs, dag ins, string opc, string asm, list<dag> pattern>
: AI<0x0, outs, ins, VFPFrm, opc, asm, pattern> { : AI<outs, ins, VFPFrm, opc, asm, pattern> {
// TODO: Mark the instructions with the appropriate subtarget info. // TODO: Mark the instructions with the appropriate subtarget info.
} }
class ASI5<dag outs, dag ins, string opc, string asm, list<dag> pattern> class ASI5<dag outs, dag ins, string opc, string asm, list<dag> pattern>
: I<0x0, outs, ins, AddrMode5, Size4Bytes, IndexModeNone, : I<outs, ins, AddrMode5, Size4Bytes, IndexModeNone,
VFPFrm, opc, asm, "", pattern> { VFPFrm, opc, asm, "", pattern> {
// TODO: Mark the instructions with the appropriate subtarget info. // TODO: Mark the instructions with the appropriate subtarget info.
} }
// ARM Double Instruction // ARM Double Instruction
class ADI<dag outs, dag ins, string opc, string asm, list<dag> pattern> class ADI<dag outs, dag ins, string opc, string asm, list<dag> pattern>
: AI<0x0, outs, ins, VFPFrm, opc, asm, pattern> { : AI<outs, ins, VFPFrm, opc, asm, pattern> {
// TODO: Mark the instructions with the appropriate subtarget info. // TODO: Mark the instructions with the appropriate subtarget info.
} }
class ADI5<dag outs, dag ins, string opc, string asm, list<dag> pattern> class ADI5<dag outs, dag ins, string opc, string asm, list<dag> pattern>
: I<0x0, outs, ins, AddrMode5, Size4Bytes, IndexModeNone, : I<outs, ins, AddrMode5, Size4Bytes, IndexModeNone,
VFPFrm, opc, asm, "", pattern> { VFPFrm, opc, asm, "", pattern> {
// TODO: Mark the instructions with the appropriate subtarget info. // TODO: Mark the instructions with the appropriate subtarget info.
} }
// Special cases. // Special cases.
class AXSI<dag outs, dag ins, string asm, list<dag> pattern> class AXSI<dag outs, dag ins, string asm, list<dag> pattern>
: XI<0x0, outs, ins, AddrModeNone, Size4Bytes, IndexModeNone, : XI<outs, ins, AddrModeNone, Size4Bytes, IndexModeNone,
VFPFrm, asm, "", pattern> { VFPFrm, asm, "", pattern> {
// TODO: Mark the instructions with the appropriate subtarget info. // TODO: Mark the instructions with the appropriate subtarget info.
} }
class AXSI5<dag outs, dag ins, string asm, list<dag> pattern> class AXSI5<dag outs, dag ins, string asm, list<dag> pattern>
: XI<0x0, outs, ins, AddrMode5, Size4Bytes, IndexModeNone, : XI<outs, ins, AddrMode5, Size4Bytes, IndexModeNone,
VFPFrm, asm, "", pattern> { VFPFrm, asm, "", pattern> {
// TODO: Mark the instructions with the appropriate subtarget info. // TODO: Mark the instructions with the appropriate subtarget info.
} }
class AXDI<dag outs, dag ins, string asm, list<dag> pattern> class AXDI<dag outs, dag ins, string asm, list<dag> pattern>
: XI<0x0, outs, ins, AddrModeNone, Size4Bytes, IndexModeNone, : XI<outs, ins, AddrModeNone, Size4Bytes, IndexModeNone,
VFPFrm, asm, "", pattern> { VFPFrm, asm, "", pattern> {
// TODO: Mark the instructions with the appropriate subtarget info. // TODO: Mark the instructions with the appropriate subtarget info.
} }
class AXDI5<dag outs, dag ins, string asm, list<dag> pattern> class AXDI5<dag outs, dag ins, string asm, list<dag> pattern>
: XI<0x0, outs, ins, AddrMode5, Size4Bytes, IndexModeNone, : XI<outs, ins, AddrMode5, Size4Bytes, IndexModeNone,
VFPFrm, asm, "", pattern> { VFPFrm, asm, "", pattern> {
// TODO: Mark the instructions with the appropriate subtarget info. // TODO: Mark the instructions with the appropriate subtarget info.
} }