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ARM cost model: Add test case to make sure we would notice a change in CodeGen

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In r176898 I updated the cost model to reflect the fact that sext/zext/cast on
v8i32 <-> v8i8 and v16i32 <-> v16i8 are expensive.

This test case is so that we make sure to update the cost model once we fix
CodeGen.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176955 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Arnold Schwaighofer 2013-03-13 16:25:55 +00:00
parent bdd2d98139
commit d8bfde0c6a
1 changed files with 153 additions and 0 deletions
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153
test/CodeGen/ARM/vcvt.ll
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@ -156,3 +156,156 @@ define <4 x i16> @vcvt_f32tof16(<4 x float>* %A) nounwind {
declare <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16>) nounwind readnone declare <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16>) nounwind readnone
declare <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float>) nounwind readnone declare <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float>) nounwind readnone
; We currently estimate the cost of sext/zext/trunc v8(v16)i32 <-> v8(v16)i8
; instructions as expensive. If lowering is improved the cost model needs to
; change.
; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -march=arm -mcpu=cortex-a8 | FileCheck %s --check-prefix=COST
%T0_5 = type <8 x i8>
%T1_5 = type <8 x i32>
; CHECK: func_cvt5:
define void @func_cvt5(%T0_5* %loadaddr, %T1_5* %storeaddr) {
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
%v0 = load %T0_5* %loadaddr
; COST: func_cvt5
; COST: cost of 24 {{.*}} sext
%r = sext %T0_5 %v0 to %T1_5
store %T1_5 %r, %T1_5* %storeaddr
ret void
}
;; We currently estimate the cost of this instruction as expensive. If lowering
;; is improved the cost needs to change.
%TA0_5 = type <8 x i8>
%TA1_5 = type <8 x i32>
; CHECK: func_cvt1:
define void @func_cvt1(%TA0_5* %loadaddr, %TA1_5* %storeaddr) {
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
%v0 = load %TA0_5* %loadaddr
; COST: func_cvt1
; COST: cost of 22 {{.*}} zext
%r = zext %TA0_5 %v0 to %TA1_5
store %TA1_5 %r, %TA1_5* %storeaddr
ret void
}
;; We currently estimate the cost of this instruction as expensive. If lowering
;; is improved the cost needs to change.
%T0_51 = type <8 x i32>
%T1_51 = type <8 x i8>
; CHECK: func_cvt51:
define void @func_cvt51(%T0_51* %loadaddr, %T1_51* %storeaddr) {
; CHECK: strb
; CHECK: strb
; CHECK: strb
; CHECK: strb
; CHECK: strb
; CHECK: strb
; CHECK: strb
; CHECK: strb
%v0 = load %T0_51* %loadaddr
; COST: func_cvt51
; COST: cost of 19 {{.*}} trunc
%r = trunc %T0_51 %v0 to %T1_51
store %T1_51 %r, %T1_51* %storeaddr
ret void
}
;; We currently estimate the cost of this instruction as expensive. If lowering
;; is improved the cost needs to change.
%TT0_5 = type <16 x i8>
%TT1_5 = type <16 x i32>
; CHECK: func_cvt52:
define void @func_cvt52(%TT0_5* %loadaddr, %TT1_5* %storeaddr) {
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
%v0 = load %TT0_5* %loadaddr
; COST: func_cvt52
; COST: cost of 48 {{.*}} sext
%r = sext %TT0_5 %v0 to %TT1_5
store %TT1_5 %r, %TT1_5* %storeaddr
ret void
}
;; We currently estimate the cost of this instruction as expensive. If lowering
;; is improved the cost needs to change.
%TTA0_5 = type <16 x i8>
%TTA1_5 = type <16 x i32>
; CHECK: func_cvt12:
define void @func_cvt12(%TTA0_5* %loadaddr, %TTA1_5* %storeaddr) {
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
; CHECK: strh
%v0 = load %TTA0_5* %loadaddr
; COST: func_cvt12
; COST: cost of 44 {{.*}} zext
%r = zext %TTA0_5 %v0 to %TTA1_5
store %TTA1_5 %r, %TTA1_5* %storeaddr
ret void
}
;; We currently estimate the cost of this instruction as expensive. If lowering
;; is improved the cost needs to change.
%TT0_51 = type <16 x i32>
%TT1_51 = type <16 x i8>
; CHECK: func_cvt512:
define void @func_cvt512(%TT0_51* %loadaddr, %TT1_51* %storeaddr) {
; CHECK: strb
; CHECK: strb
; CHECK: strb
; CHECK: strb
; CHECK: strb
; CHECK: strb
; CHECK: strb
; CHECK: strb
; CHECK: strb
; CHECK: strb
; CHECK: strb
; CHECK: strb
; CHECK: strb
; CHECK: strb
; CHECK: strb
; CHECK: strb
%v0 = load %TT0_51* %loadaddr
; COST: func_cvt512
; COST: cost of 38 {{.*}} trunc
%r = trunc %TT0_51 %v0 to %TT1_51
store %TT1_51 %r, %TT1_51* %storeaddr
ret void
}