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VLDR fixups need special handling under Thumb. While the encoding is the same,

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the order of the bytes in the data stream is flipped around.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121215 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
2010-12-08 00:18:36 +00:00
parent e113ae56d9
commit d8e351b96f
3 changed files with 23 additions and 2 deletions
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12
lib/Target/ARM/ARMAsmBackend.cpp
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@ -115,6 +115,7 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
Binary = ((Binary & 0x7ff) << 16) | (Binary >> 11);
return Binary;
}
case ARM::fixup_t2_pcrel_10:
case ARM::fixup_arm_pcrel_10: {
// Offset by 8 just as above.
Value = Value - 8;
@ -127,6 +128,16 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
Value >>= 2;
assert ((Value < 256) && "Out of range pc-relative fixup value!");
Value |= isAdd << 23;
// Same addressing mode as fixup_arm_pcrel_10, but with the bytes reordered.
if (Kind == ARM::fixup_t2_pcrel_10) {
uint64_t swapped = (Value & 0x00FF0000) >> 16;
swapped |= (Value & 0xFF000000) >> 16;
swapped |= (Value & 0x000000FF) << 16;
swapped |= (Value & 0x0000FF00) << 16;
return swapped;
}
return Value;
}
}
@ -218,6 +229,7 @@ static unsigned getFixupKindNumBytes(unsigned Kind) {
case ARM::fixup_arm_adr_pcrel_12:
case ARM::fixup_arm_branch:
return 3;
case ARM::fixup_t2_pcrel_10:
case ARM::fixup_arm_thumb_bl:
return 4;
}