R600/SI: Add pattern for bitcasting fp immediates to integers

The backend now assumes that all immediates are integers.  This allows
us to simplify immediate handling code, becasue we no longer need to
handle fp and integer immediates differently.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225844 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
2015-01-13 22:59:41 +00:00
parent a28a251950
commit d90e5063ca
8 changed files with 39 additions and 56 deletions

View File

@@ -130,7 +130,7 @@ static void foldImmediates(MachineInstr &MI, const SIInstrInfo *TII,
// Only one literal constant is allowed per instruction, so if src0 is a
// literal constant then we can't do any folding.
if ((Src0->isImm() || Src0->isFPImm()) && TII->isLiteralConstant(*Src0))
if (Src0->isImm() && TII->isLiteralConstant(*Src0))
return;
@@ -151,12 +151,6 @@ static void foldImmediates(MachineInstr &MI, const SIInstrInfo *TII,
if (MovSrc.isImm() && isUInt<32>(MovSrc.getImm())) {
Src0->ChangeToImmediate(MovSrc.getImm());
ConstantFolded = true;
} else if (MovSrc.isFPImm()) {
const ConstantFP *CFP = MovSrc.getFPImm();
if (&CFP->getValueAPF().getSemantics() == &APFloat::IEEEsingle) {
Src0->ChangeToFPImmediate(CFP);
ConstantFolded = true;
}
}
if (ConstantFolded) {
if (MRI.use_empty(Reg))
@@ -193,7 +187,6 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) {
if (MI.getOpcode() == AMDGPU::S_MOV_B32) {
const MachineOperand &Src = MI.getOperand(1);
// TODO: Handle FPImm?
if (Src.isImm()) {
if (isInt<16>(Src.getImm()) && !TII->isInlineConstant(Src))
MI.setDesc(TII->get(AMDGPU::S_MOVK_I32));