From d92354c5742ea72abd3039cda5be37cc757d47d2 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Tue, 9 Nov 2010 17:38:15 +0000 Subject: [PATCH] For ARM load/store instructions, encode [reg+reg] with no shifter immediate as a left shift by zero. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118587 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMMCCodeEmitter.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp index 7b0bf12bffc..bd799f233c0 100644 --- a/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -277,6 +277,9 @@ getLdStSORegOpValue(const MCInst &MI, unsigned OpIdx, // ROR - 11 switch (ShOp) { default: llvm_unreachable("Unknown shift opc!"); + case ARM_AM::no_shift: + assert(ShImm == 0 && "Non-zero shift amount with no shift type!"); + // fall through case ARM_AM::lsl: SBits = 0x0; break; case ARM_AM::lsr: SBits = 0x1; break; case ARM_AM::asr: SBits = 0x2; break;