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Code clean up.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85046 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2009-10-25 07:49:57 +00:00
parent d66f0015ad
commit d98e30f618
1 changed files with 33 additions and 33 deletions
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66
lib/CodeGen/LowerSubregs.cpp
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@ -30,6 +30,11 @@ using namespace llvm;
namespace { namespace {
struct LowerSubregsInstructionPass : public MachineFunctionPass { struct LowerSubregsInstructionPass : public MachineFunctionPass {
private:
const TargetRegisterInfo *TRI;
const TargetInstrInfo *TII;
public:
static char ID; // Pass identification, replacement for typeid static char ID; // Pass identification, replacement for typeid
LowerSubregsInstructionPass() : MachineFunctionPass(&ID) {} LowerSubregsInstructionPass() : MachineFunctionPass(&ID) {}
@ -46,15 +51,16 @@ namespace {
/// runOnMachineFunction - pass entry point /// runOnMachineFunction - pass entry point
bool runOnMachineFunction(MachineFunction&); bool runOnMachineFunction(MachineFunction&);
private:
bool LowerExtract(MachineInstr *MI); bool LowerExtract(MachineInstr *MI);
bool LowerInsert(MachineInstr *MI); bool LowerInsert(MachineInstr *MI);
bool LowerSubregToReg(MachineInstr *MI); bool LowerSubregToReg(MachineInstr *MI);
void TransferDeadFlag(MachineInstr *MI, unsigned DstReg, void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
const TargetRegisterInfo &TRI); const TargetRegisterInfo *TRI);
void TransferKillFlag(MachineInstr *MI, unsigned SrcReg, void TransferKillFlag(MachineInstr *MI, unsigned SrcReg,
const TargetRegisterInfo &TRI, const TargetRegisterInfo *TRI,
bool AddIfNotFound = false); bool AddIfNotFound = false);
}; };
@ -71,10 +77,10 @@ FunctionPass *llvm::createLowerSubregsPass() {
void void
LowerSubregsInstructionPass::TransferDeadFlag(MachineInstr *MI, LowerSubregsInstructionPass::TransferDeadFlag(MachineInstr *MI,
unsigned DstReg, unsigned DstReg,
const TargetRegisterInfo &TRI) { const TargetRegisterInfo *TRI) {
for (MachineBasicBlock::iterator MII = for (MachineBasicBlock::iterator MII =
prior(MachineBasicBlock::iterator(MI)); ; --MII) { prior(MachineBasicBlock::iterator(MI)); ; --MII) {
if (MII->addRegisterDead(DstReg, &TRI)) if (MII->addRegisterDead(DstReg, TRI))
break; break;
assert(MII != MI->getParent()->begin() && assert(MII != MI->getParent()->begin() &&
"copyRegToReg output doesn't reference destination register!"); "copyRegToReg output doesn't reference destination register!");
@ -87,11 +93,11 @@ LowerSubregsInstructionPass::TransferDeadFlag(MachineInstr *MI,
void void
LowerSubregsInstructionPass::TransferKillFlag(MachineInstr *MI, LowerSubregsInstructionPass::TransferKillFlag(MachineInstr *MI,
unsigned SrcReg, unsigned SrcReg,
const TargetRegisterInfo &TRI, const TargetRegisterInfo *TRI,
bool AddIfNotFound) { bool AddIfNotFound) {
for (MachineBasicBlock::iterator MII = for (MachineBasicBlock::iterator MII =
prior(MachineBasicBlock::iterator(MI)); ; --MII) { prior(MachineBasicBlock::iterator(MI)); ; --MII) {
if (MII->addRegisterKilled(SrcReg, &TRI, AddIfNotFound)) if (MII->addRegisterKilled(SrcReg, TRI, AddIfNotFound))
break; break;
assert(MII != MI->getParent()->begin() && assert(MII != MI->getParent()->begin() &&
"copyRegToReg output doesn't reference source register!"); "copyRegToReg output doesn't reference source register!");
@ -100,9 +106,6 @@ LowerSubregsInstructionPass::TransferKillFlag(MachineInstr *MI,
bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) { bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
MachineBasicBlock *MBB = MI->getParent(); MachineBasicBlock *MBB = MI->getParent();
MachineFunction &MF = *MBB->getParent();
const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
assert(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() && assert(MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
MI->getOperand(1).isReg() && MI->getOperand(1).isUse() && MI->getOperand(1).isReg() && MI->getOperand(1).isUse() &&
@ -111,7 +114,7 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
unsigned DstReg = MI->getOperand(0).getReg(); unsigned DstReg = MI->getOperand(0).getReg();
unsigned SuperReg = MI->getOperand(1).getReg(); unsigned SuperReg = MI->getOperand(1).getReg();
unsigned SubIdx = MI->getOperand(2).getImm(); unsigned SubIdx = MI->getOperand(2).getImm();
unsigned SrcReg = TRI.getSubReg(SuperReg, SubIdx); unsigned SrcReg = TRI->getSubReg(SuperReg, SubIdx);
assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) && assert(TargetRegisterInfo::isPhysicalRegister(SuperReg) &&
"Extract supperg source must be a physical register"); "Extract supperg source must be a physical register");
@ -126,7 +129,7 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
if (MI->getOperand(1).isKill()) { if (MI->getOperand(1).isKill()) {
// We must make sure the super-register gets killed. Replace the // We must make sure the super-register gets killed. Replace the
// instruction with KILL. // instruction with KILL.
MI->setDesc(TII.get(TargetInstrInfo::KILL)); MI->setDesc(TII->get(TargetInstrInfo::KILL));
MI->RemoveOperand(2); // SubIdx MI->RemoveOperand(2); // SubIdx
DEBUG(errs() << "subreg: replace by: " << *MI); DEBUG(errs() << "subreg: replace by: " << *MI);
return true; return true;
@ -135,9 +138,9 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
DEBUG(errs() << "subreg: eliminated!"); DEBUG(errs() << "subreg: eliminated!");
} else { } else {
// Insert copy // Insert copy
const TargetRegisterClass *TRCS = TRI.getPhysicalRegisterRegClass(DstReg); const TargetRegisterClass *TRCS = TRI->getPhysicalRegisterRegClass(DstReg);
const TargetRegisterClass *TRCD = TRI.getPhysicalRegisterRegClass(SrcReg); const TargetRegisterClass *TRCD = TRI->getPhysicalRegisterRegClass(SrcReg);
bool Emitted = TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRCD, TRCS); bool Emitted = TII->copyRegToReg(*MBB, MI, DstReg, SrcReg, TRCD, TRCS);
(void)Emitted; (void)Emitted;
assert(Emitted && "Subreg and Dst must be of compatible register class"); assert(Emitted && "Subreg and Dst must be of compatible register class");
// Transfer the kill/dead flags, if needed. // Transfer the kill/dead flags, if needed.
@ -158,9 +161,6 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) { bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
MachineBasicBlock *MBB = MI->getParent(); MachineBasicBlock *MBB = MI->getParent();
MachineFunction &MF = *MBB->getParent();
const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
MI->getOperand(1).isImm() && MI->getOperand(1).isImm() &&
(MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
@ -172,7 +172,7 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
unsigned SubIdx = MI->getOperand(3).getImm(); unsigned SubIdx = MI->getOperand(3).getImm();
assert(SubIdx != 0 && "Invalid index for insert_subreg"); assert(SubIdx != 0 && "Invalid index for insert_subreg");
unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx); unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
assert(TargetRegisterInfo::isPhysicalRegister(DstReg) && assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
"Insert destination must be in a physical register"); "Insert destination must be in a physical register");
@ -191,9 +191,9 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
DEBUG(errs() << "subreg: eliminated!"); DEBUG(errs() << "subreg: eliminated!");
} else { } else {
// Insert sub-register copy // Insert sub-register copy
const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg); const TargetRegisterClass *TRC0= TRI->getPhysicalRegisterRegClass(DstSubReg);
const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg); const TargetRegisterClass *TRC1= TRI->getPhysicalRegisterRegClass(InsReg);
bool Emitted = TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1); bool Emitted = TII->copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
(void)Emitted; (void)Emitted;
assert(Emitted && "Subreg and Dst must be of compatible register class"); assert(Emitted && "Subreg and Dst must be of compatible register class");
// Transfer the kill/dead flags, if needed. // Transfer the kill/dead flags, if needed.
@ -214,9 +214,6 @@ bool LowerSubregsInstructionPass::LowerSubregToReg(MachineInstr *MI) {
bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) { bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
MachineBasicBlock *MBB = MI->getParent(); MachineBasicBlock *MBB = MI->getParent();
MachineFunction &MF = *MBB->getParent();
const TargetRegisterInfo &TRI = *MF.getTarget().getRegisterInfo();
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) &&
(MI->getOperand(1).isReg() && MI->getOperand(1).isUse()) && (MI->getOperand(1).isReg() && MI->getOperand(1).isUse()) &&
(MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
@ -231,7 +228,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
assert(DstReg == SrcReg && "insert_subreg not a two-address instruction?"); assert(DstReg == SrcReg && "insert_subreg not a two-address instruction?");
assert(SubIdx != 0 && "Invalid index for insert_subreg"); assert(SubIdx != 0 && "Invalid index for insert_subreg");
unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx); unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx);
assert(DstSubReg && "invalid subregister index for register"); assert(DstSubReg && "invalid subregister index for register");
assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) && assert(TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
"Insert superreg source must be in a physical register"); "Insert superreg source must be in a physical register");
@ -245,7 +242,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
// <undef>, we need to make sure it is alive by inserting a KILL // <undef>, we need to make sure it is alive by inserting a KILL
if (MI->getOperand(1).isUndef() && !MI->getOperand(0).isDead()) { if (MI->getOperand(1).isUndef() && !MI->getOperand(0).isDead()) {
MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
TII.get(TargetInstrInfo::KILL), DstReg); TII->get(TargetInstrInfo::KILL), DstReg);
if (MI->getOperand(2).isUndef()) if (MI->getOperand(2).isUndef())
MIB.addReg(InsReg, RegState::Undef); MIB.addReg(InsReg, RegState::Undef);
else else
@ -257,15 +254,15 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
} }
} else { } else {
// Insert sub-register copy // Insert sub-register copy
const TargetRegisterClass *TRC0= TRI.getPhysicalRegisterRegClass(DstSubReg); const TargetRegisterClass *TRC0= TRI->getPhysicalRegisterRegClass(DstSubReg);
const TargetRegisterClass *TRC1= TRI.getPhysicalRegisterRegClass(InsReg); const TargetRegisterClass *TRC1= TRI->getPhysicalRegisterRegClass(InsReg);
if (MI->getOperand(2).isUndef()) if (MI->getOperand(2).isUndef())
// If the source register being inserted is undef, then this becomes a // If the source register being inserted is undef, then this becomes a
// KILL. // KILL.
BuildMI(*MBB, MI, MI->getDebugLoc(), BuildMI(*MBB, MI, MI->getDebugLoc(),
TII.get(TargetInstrInfo::KILL), DstSubReg); TII->get(TargetInstrInfo::KILL), DstSubReg);
else { else {
bool Emitted = TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1); bool Emitted = TII->copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC0, TRC1);
(void)Emitted; (void)Emitted;
assert(Emitted && "Subreg and Dst must be of compatible register class"); assert(Emitted && "Subreg and Dst must be of compatible register class");
} }
@ -306,6 +303,8 @@ bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
<< "********** LOWERING SUBREG INSTRS **********\n" << "********** LOWERING SUBREG INSTRS **********\n"
<< "********** Function: " << "********** Function: "
<< MF.getFunction()->getName() << '\n'); << MF.getFunction()->getName() << '\n');
TRI = MF.getTarget().getRegisterInfo();
TII = MF.getTarget().getInstrInfo();
bool MadeChange = false; bool MadeChange = false;
@ -313,8 +312,8 @@ bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
mbbi != mbbe; ++mbbi) { mbbi != mbbe; ++mbbi) {
for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end(); for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
mi != me;) { mi != me;) {
MachineInstr *MI = mi++; MachineBasicBlock::iterator nmi = next(mi);
MachineInstr *MI = mi;
if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) { if (MI->getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
MadeChange |= LowerExtract(MI); MadeChange |= LowerExtract(MI);
} else if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) { } else if (MI->getOpcode() == TargetInstrInfo::INSERT_SUBREG) {
@ -322,6 +321,7 @@ bool LowerSubregsInstructionPass::runOnMachineFunction(MachineFunction &MF) {
} else if (MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) { } else if (MI->getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
MadeChange |= LowerSubregToReg(MI); MadeChange |= LowerSubregToReg(MI);
} }
mi = nmi;
} }
} }