mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Add IIC_ prefix to PPC instruction-class names
This adds the IIC_ prefix to the instruction itinerary class names, giving the PPC backend a naming convention for itinerary classes that is more consistent with that used by the X86 and ARM backends. Instruction scheduling in the PPC backend needs a bunch of cleanup and improvement (especially for the ooo cores). This is just a preliminary step. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195890 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel
@@ -83,12 +83,14 @@ def HI48_64 : SDNodeXForm<imm, [{
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let Interpretation64Bit = 1 in {
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let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
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let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
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def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
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def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
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[]>,
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Requires<[In64BitMode]>;
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let isCodeGenOnly = 1 in
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def BCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
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"b${cond:cc}ctr${cond:pm} ${cond:reg}", BrB, []>,
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"b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
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[]>,
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Requires<[In64BitMode]>;
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}
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}
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@@ -107,9 +109,9 @@ let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
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let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
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def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
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"bdzlr", BrB, []>;
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"bdzlr", IIC_BrB, []>;
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def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
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"bdnzlr", BrB, []>;
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"bdnzlr", IIC_BrB, []>;
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}
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}
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@@ -119,36 +121,37 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
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// Convenient aliases for call instructions
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let Uses = [RM] in {
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def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
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"bl $func", BrB, []>; // See Pat patterns below.
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"bl $func", IIC_BrB, []>; // See Pat patterns below.
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def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func),
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"bl $func", BrB, []>;
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"bl $func", IIC_BrB, []>;
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def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
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"bla $func", BrB, [(PPCcall (i64 imm:$func))]>;
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"bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>;
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}
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let Uses = [RM], isCodeGenOnly = 1 in {
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def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
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(outs), (ins calltarget:$func),
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"bl $func\n\tnop", BrB, []>;
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"bl $func\n\tnop", IIC_BrB, []>;
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def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24,
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(outs), (ins tlscall:$func),
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"bl $func\n\tnop", BrB, []>;
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"bl $func\n\tnop", IIC_BrB, []>;
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def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
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(outs), (ins abscalltarget:$func),
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"bla $func\n\tnop", BrB,
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"bla $func\n\tnop", IIC_BrB,
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[(PPCcall_nop (i64 imm:$func))]>;
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}
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let Uses = [CTR8, RM] in {
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def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
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"bctrl", BrB, [(PPCbctrl)]>,
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"bctrl", IIC_BrB, [(PPCbctrl)]>,
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Requires<[In64BitMode]>;
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let isCodeGenOnly = 1 in
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def BCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
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"b${cond:cc}ctrl${cond:pm} ${cond:reg}", BrB, []>,
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"b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
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[]>,
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Requires<[In64BitMode]>;
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}
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}
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@@ -199,12 +202,12 @@ let usesCustomInserter = 1 in {
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// Instructions to support atomic operations
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def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
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"ldarx $rD, $ptr", LdStLDARX,
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"ldarx $rD, $ptr", IIC_LdStLDARX,
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[(set i64:$rD, (PPClarx xoaddr:$ptr))]>;
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let Defs = [CR0] in
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def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
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"stdcx. $rS, $dst", LdStSTDCX,
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"stdcx. $rS, $dst", IIC_LdStSTDCX,
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[(PPCstcx i64:$rS, xoaddr:$dst)]>,
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isDOT;
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@@ -229,21 +232,22 @@ let isCodeGenOnly = 1 in {
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let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
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isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
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def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
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def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
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[]>,
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Requires<[In64BitMode]>;
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let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
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isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
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def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
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"b $dst", BrB,
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"b $dst", IIC_BrB,
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[]>;
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let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
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isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
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def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
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"ba $dst", BrB,
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"ba $dst", IIC_BrB,
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[]>;
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}
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@@ -263,20 +267,20 @@ def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
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let Interpretation64Bit = 1 in {
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let neverHasSideEffects = 1 in {
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def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST),
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"mtocrf $FXM, $ST", BrMCRX>,
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"mtocrf $FXM, $ST", IIC_BrMCRX>,
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PPC970_DGroup_First, PPC970_Unit_CRU;
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def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS),
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"mtcrf $FXM, $rS", BrMCRX>,
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"mtcrf $FXM, $rS", IIC_BrMCRX>,
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PPC970_MicroCode, PPC970_Unit_CRU;
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let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
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def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM),
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"mfocrf $rT, $FXM", SprMFCR>,
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"mfocrf $rT, $FXM", IIC_SprMFCR>,
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PPC970_DGroup_First, PPC970_Unit_CRU;
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def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins),
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"mfcr $rT", SprMFCR>,
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"mfcr $rT", IIC_SprMFCR>,
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PPC970_MicroCode, PPC970_Unit_CRU;
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} // neverHasSideEffects = 1
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@@ -298,24 +302,24 @@ let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
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let Uses = [CTR8] in {
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def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins),
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"mfctr $rT", SprMFSPR>,
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"mfctr $rT", IIC_SprMFSPR>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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}
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let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in {
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def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
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"mtctr $rS", SprMTSPR>,
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"mtctr $rS", IIC_SprMTSPR>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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}
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let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR8] in {
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let Pattern = [(int_ppc_mtctr i64:$rS)] in
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def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
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"mtctr $rS", SprMTSPR>,
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"mtctr $rS", IIC_SprMTSPR>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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}
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let isCodeGenOnly = 1, Pattern = [(set i64:$rT, readcyclecounter)] in
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def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins),
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"mfspr $rT, 268", SprMFTB>,
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"mfspr $rT, 268", IIC_SprMFTB>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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// Note that encoding mftb using mfspr is now the preferred form,
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// and has been since at least ISA v2.03. The mftb instruction has
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@@ -329,12 +333,12 @@ def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#D
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let Defs = [LR8] in {
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def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS),
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"mtlr $rS", SprMTSPR>,
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"mtlr $rS", IIC_SprMTSPR>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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}
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let Uses = [LR8] in {
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def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins),
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"mflr $rT", SprMFSPR>,
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"mflr $rT", IIC_SprMFSPR>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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}
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} // Interpretation64Bit
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@@ -349,210 +353,211 @@ let neverHasSideEffects = 1 in {
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let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
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def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm),
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"li $rD, $imm", IntSimple,
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"li $rD, $imm", IIC_IntSimple,
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[(set i64:$rD, imm64SExt16:$imm)]>;
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def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm),
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"lis $rD, $imm", IntSimple,
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"lis $rD, $imm", IIC_IntSimple,
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[(set i64:$rD, imm16ShiftedSExt:$imm)]>;
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}
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// Logical ops.
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defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
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"nand", "$rA, $rS, $rB", IntSimple,
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"nand", "$rA, $rS, $rB", IIC_IntSimple,
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[(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
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defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
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"and", "$rA, $rS, $rB", IntSimple,
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"and", "$rA, $rS, $rB", IIC_IntSimple,
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[(set i64:$rA, (and i64:$rS, i64:$rB))]>;
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defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
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"andc", "$rA, $rS, $rB", IntSimple,
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"andc", "$rA, $rS, $rB", IIC_IntSimple,
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[(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>;
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defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
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"or", "$rA, $rS, $rB", IntSimple,
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"or", "$rA, $rS, $rB", IIC_IntSimple,
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[(set i64:$rA, (or i64:$rS, i64:$rB))]>;
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defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
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"nor", "$rA, $rS, $rB", IntSimple,
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"nor", "$rA, $rS, $rB", IIC_IntSimple,
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[(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>;
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defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
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"orc", "$rA, $rS, $rB", IntSimple,
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"orc", "$rA, $rS, $rB", IIC_IntSimple,
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[(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>;
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defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
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"eqv", "$rA, $rS, $rB", IntSimple,
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"eqv", "$rA, $rS, $rB", IIC_IntSimple,
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[(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
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defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
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"xor", "$rA, $rS, $rB", IntSimple,
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"xor", "$rA, $rS, $rB", IIC_IntSimple,
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[(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
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// Logical ops with immediate.
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let Defs = [CR0] in {
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def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
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"andi. $dst, $src1, $src2", IntGeneral,
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"andi. $dst, $src1, $src2", IIC_IntGeneral,
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[(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
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isDOT;
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def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
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"andis. $dst, $src1, $src2", IntGeneral,
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"andis. $dst, $src1, $src2", IIC_IntGeneral,
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[(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
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isDOT;
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}
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def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
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"ori $dst, $src1, $src2", IntSimple,
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"ori $dst, $src1, $src2", IIC_IntSimple,
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[(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
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def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
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"oris $dst, $src1, $src2", IntSimple,
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"oris $dst, $src1, $src2", IIC_IntSimple,
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[(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
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def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
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"xori $dst, $src1, $src2", IntSimple,
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"xori $dst, $src1, $src2", IIC_IntSimple,
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[(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>;
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def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
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"xoris $dst, $src1, $src2", IntSimple,
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"xoris $dst, $src1, $src2", IIC_IntSimple,
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[(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>;
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defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
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"add", "$rT, $rA, $rB", IntSimple,
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"add", "$rT, $rA, $rB", IIC_IntSimple,
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[(set i64:$rT, (add i64:$rA, i64:$rB))]>;
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// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
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// initial-exec thread-local storage model.
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def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
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"add $rT, $rA, $rB", IntSimple,
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"add $rT, $rA, $rB", IIC_IntSimple,
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[(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>;
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defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
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"addc", "$rT, $rA, $rB", IntGeneral,
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"addc", "$rT, $rA, $rB", IIC_IntGeneral,
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[(set i64:$rT, (addc i64:$rA, i64:$rB))]>,
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PPC970_DGroup_Cracked;
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let Defs = [CARRY] in
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def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
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"addic $rD, $rA, $imm", IntGeneral,
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"addic $rD, $rA, $imm", IIC_IntGeneral,
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[(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>;
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def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm),
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"addi $rD, $rA, $imm", IntSimple,
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"addi $rD, $rA, $imm", IIC_IntSimple,
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[(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>;
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def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm),
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"addis $rD, $rA, $imm", IntSimple,
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"addis $rD, $rA, $imm", IIC_IntSimple,
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[(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>;
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let Defs = [CARRY] in {
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def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
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"subfic $rD, $rA, $imm", IntGeneral,
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"subfic $rD, $rA, $imm", IIC_IntGeneral,
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[(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>;
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defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
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"subfc", "$rT, $rA, $rB", IntGeneral,
|
||||
"subfc", "$rT, $rA, $rB", IIC_IntGeneral,
|
||||
[(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
|
||||
PPC970_DGroup_Cracked;
|
||||
}
|
||||
defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
|
||||
"subf", "$rT, $rA, $rB", IntGeneral,
|
||||
"subf", "$rT, $rA, $rB", IIC_IntGeneral,
|
||||
[(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
|
||||
defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA),
|
||||
"neg", "$rT, $rA", IntSimple,
|
||||
"neg", "$rT, $rA", IIC_IntSimple,
|
||||
[(set i64:$rT, (ineg i64:$rA))]>;
|
||||
let Uses = [CARRY] in {
|
||||
defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
|
||||
"adde", "$rT, $rA, $rB", IntGeneral,
|
||||
"adde", "$rT, $rA, $rB", IIC_IntGeneral,
|
||||
[(set i64:$rT, (adde i64:$rA, i64:$rB))]>;
|
||||
defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA),
|
||||
"addme", "$rT, $rA", IntGeneral,
|
||||
"addme", "$rT, $rA", IIC_IntGeneral,
|
||||
[(set i64:$rT, (adde i64:$rA, -1))]>;
|
||||
defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA),
|
||||
"addze", "$rT, $rA", IntGeneral,
|
||||
"addze", "$rT, $rA", IIC_IntGeneral,
|
||||
[(set i64:$rT, (adde i64:$rA, 0))]>;
|
||||
defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
|
||||
"subfe", "$rT, $rA, $rB", IntGeneral,
|
||||
"subfe", "$rT, $rA, $rB", IIC_IntGeneral,
|
||||
[(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
|
||||
defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA),
|
||||
"subfme", "$rT, $rA", IntGeneral,
|
||||
"subfme", "$rT, $rA", IIC_IntGeneral,
|
||||
[(set i64:$rT, (sube -1, i64:$rA))]>;
|
||||
defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA),
|
||||
"subfze", "$rT, $rA", IntGeneral,
|
||||
"subfze", "$rT, $rA", IIC_IntGeneral,
|
||||
[(set i64:$rT, (sube 0, i64:$rA))]>;
|
||||
}
|
||||
|
||||
|
||||
defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
|
||||
"mulhd", "$rT, $rA, $rB", IntMulHW,
|
||||
"mulhd", "$rT, $rA, $rB", IIC_IntMulHW,
|
||||
[(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
|
||||
defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
|
||||
"mulhdu", "$rT, $rA, $rB", IntMulHWU,
|
||||
"mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU,
|
||||
[(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
|
||||
}
|
||||
} // Interpretation64Bit
|
||||
|
||||
let isCompare = 1, neverHasSideEffects = 1 in {
|
||||
def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
|
||||
"cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
|
||||
"cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64;
|
||||
def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
|
||||
"cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
|
||||
"cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64;
|
||||
def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm:$imm),
|
||||
"cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
|
||||
"cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64;
|
||||
def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm:$src2),
|
||||
"cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
|
||||
"cmpldi $dst, $src1, $src2",
|
||||
IIC_IntCompare>, isPPC64;
|
||||
}
|
||||
|
||||
let neverHasSideEffects = 1 in {
|
||||
defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
|
||||
"sld", "$rA, $rS, $rB", IntRotateD,
|
||||
"sld", "$rA, $rS, $rB", IIC_IntRotateD,
|
||||
[(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64;
|
||||
defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
|
||||
"srd", "$rA, $rS, $rB", IntRotateD,
|
||||
"srd", "$rA, $rS, $rB", IIC_IntRotateD,
|
||||
[(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64;
|
||||
defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
|
||||
"srad", "$rA, $rS, $rB", IntRotateD,
|
||||
"srad", "$rA, $rS, $rB", IIC_IntRotateD,
|
||||
[(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64;
|
||||
|
||||
let Interpretation64Bit = 1 in {
|
||||
defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS),
|
||||
"extsb", "$rA, $rS", IntSimple,
|
||||
"extsb", "$rA, $rS", IIC_IntSimple,
|
||||
[(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
|
||||
defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS),
|
||||
"extsh", "$rA, $rS", IntSimple,
|
||||
"extsh", "$rA, $rS", IIC_IntSimple,
|
||||
[(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
|
||||
} // Interpretation64Bit
|
||||
|
||||
// For fast-isel:
|
||||
let isCodeGenOnly = 1 in {
|
||||
def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS),
|
||||
"extsb $rA, $rS", IntSimple, []>, isPPC64;
|
||||
"extsb $rA, $rS", IIC_IntSimple, []>, isPPC64;
|
||||
def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS),
|
||||
"extsh $rA, $rS", IntSimple, []>, isPPC64;
|
||||
"extsh $rA, $rS", IIC_IntSimple, []>, isPPC64;
|
||||
} // isCodeGenOnly for fast-isel
|
||||
|
||||
defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS),
|
||||
"extsw", "$rA, $rS", IntSimple,
|
||||
"extsw", "$rA, $rS", IIC_IntSimple,
|
||||
[(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
|
||||
let Interpretation64Bit = 1 in
|
||||
defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
|
||||
"extsw", "$rA, $rS", IntSimple,
|
||||
"extsw", "$rA, $rS", IIC_IntSimple,
|
||||
[(set i64:$rA, (sext i32:$rS))]>, isPPC64;
|
||||
|
||||
defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
|
||||
"sradi", "$rA, $rS, $SH", IntRotateDI,
|
||||
"sradi", "$rA, $rS, $SH", IIC_IntRotateDI,
|
||||
[(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
|
||||
defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
|
||||
"cntlzd", "$rA, $rS", IntGeneral,
|
||||
"cntlzd", "$rA, $rS", IIC_IntGeneral,
|
||||
[(set i64:$rA, (ctlz i64:$rS))]>;
|
||||
def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
|
||||
"popcntd $rA, $rS", IntGeneral,
|
||||
"popcntd $rA, $rS", IIC_IntGeneral,
|
||||
[(set i64:$rA, (ctpop i64:$rS))]>;
|
||||
|
||||
// popcntw also does a population count on the high 32 bits (storing the
|
||||
// results in the high 32-bits of the output). We'll ignore that here (which is
|
||||
// safe because we never separately use the high part of the 64-bit registers).
|
||||
def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS),
|
||||
"popcntw $rA, $rS", IntGeneral,
|
||||
"popcntw $rA, $rS", IIC_IntGeneral,
|
||||
[(set i32:$rA, (ctpop i32:$rS))]>;
|
||||
|
||||
defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
|
||||
"divd", "$rT, $rA, $rB", IntDivD,
|
||||
"divd", "$rT, $rA, $rB", IIC_IntDivD,
|
||||
[(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64,
|
||||
PPC970_DGroup_First, PPC970_DGroup_Cracked;
|
||||
defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
|
||||
"divdu", "$rT, $rA, $rB", IntDivD,
|
||||
"divdu", "$rT, $rA, $rB", IIC_IntDivD,
|
||||
[(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64,
|
||||
PPC970_DGroup_First, PPC970_DGroup_Cracked;
|
||||
defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
|
||||
"mulld", "$rT, $rA, $rB", IntMulHD,
|
||||
"mulld", "$rT, $rA, $rB", IIC_IntMulHD,
|
||||
[(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
|
||||
def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
|
||||
"mulli $rD, $rA, $imm", IntMulLI,
|
||||
"mulli $rD, $rA, $imm", IIC_IntMulLI,
|
||||
[(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>;
|
||||
}
|
||||
|
||||
@@ -560,7 +565,7 @@ let neverHasSideEffects = 1 in {
|
||||
let isCommutable = 1 in {
|
||||
defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA),
|
||||
(ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE),
|
||||
"rldimi", "$rA, $rS, $SH, $MBE", IntRotateDI,
|
||||
"rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
|
||||
[]>, isPPC64, RegConstraint<"$rSi = $rA">,
|
||||
NoEncode<"$rSi">;
|
||||
}
|
||||
@@ -568,43 +573,43 @@ defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA),
|
||||
// Rotate instructions.
|
||||
defm RLDCL : MDSForm_1r<30, 8,
|
||||
(outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
|
||||
"rldcl", "$rA, $rS, $rB, $MBE", IntRotateD,
|
||||
"rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD,
|
||||
[]>, isPPC64;
|
||||
defm RLDCR : MDSForm_1r<30, 9,
|
||||
(outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
|
||||
"rldcr", "$rA, $rS, $rB, $MBE", IntRotateD,
|
||||
"rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD,
|
||||
[]>, isPPC64;
|
||||
defm RLDICL : MDForm_1r<30, 0,
|
||||
(outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
|
||||
"rldicl", "$rA, $rS, $SH, $MBE", IntRotateDI,
|
||||
"rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
|
||||
[]>, isPPC64;
|
||||
// For fast-isel:
|
||||
let isCodeGenOnly = 1 in
|
||||
def RLDICL_32_64 : MDForm_1<30, 0,
|
||||
(outs g8rc:$rA),
|
||||
(ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
|
||||
"rldicl $rA, $rS, $SH, $MBE", IntRotateDI,
|
||||
"rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI,
|
||||
[]>, isPPC64;
|
||||
// End fast-isel.
|
||||
defm RLDICR : MDForm_1r<30, 1,
|
||||
(outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
|
||||
"rldicr", "$rA, $rS, $SH, $MBE", IntRotateDI,
|
||||
"rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
|
||||
[]>, isPPC64;
|
||||
defm RLDIC : MDForm_1r<30, 2,
|
||||
(outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
|
||||
"rldic", "$rA, $rS, $SH, $MBE", IntRotateDI,
|
||||
"rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
|
||||
[]>, isPPC64;
|
||||
|
||||
let Interpretation64Bit = 1 in {
|
||||
defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA),
|
||||
(ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
|
||||
"rlwinm", "$rA, $rS, $SH, $MB, $ME", IntGeneral,
|
||||
"rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
|
||||
[]>;
|
||||
|
||||
let isSelect = 1 in
|
||||
def ISEL8 : AForm_4<31, 15,
|
||||
(outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond),
|
||||
"isel $rT, $rA, $rB, $cond", IntGeneral,
|
||||
"isel $rT, $rA, $rB, $cond", IIC_IntGeneral,
|
||||
[]>;
|
||||
} // Interpretation64Bit
|
||||
} // neverHasSideEffects = 1
|
||||
@@ -620,30 +625,30 @@ def ISEL8 : AForm_4<31, 15,
|
||||
let canFoldAsLoad = 1, PPC970_Unit = 2 in {
|
||||
let Interpretation64Bit = 1 in
|
||||
def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src),
|
||||
"lha $rD, $src", LdStLHA,
|
||||
"lha $rD, $src", IIC_LdStLHA,
|
||||
[(set i64:$rD, (sextloadi16 iaddr:$src))]>,
|
||||
PPC970_DGroup_Cracked;
|
||||
def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src),
|
||||
"lwa $rD, $src", LdStLWA,
|
||||
"lwa $rD, $src", IIC_LdStLWA,
|
||||
[(set i64:$rD,
|
||||
(aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
|
||||
PPC970_DGroup_Cracked;
|
||||
let Interpretation64Bit = 1 in
|
||||
def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src),
|
||||
"lhax $rD, $src", LdStLHA,
|
||||
"lhax $rD, $src", IIC_LdStLHA,
|
||||
[(set i64:$rD, (sextloadi16 xaddr:$src))]>,
|
||||
PPC970_DGroup_Cracked;
|
||||
def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src),
|
||||
"lwax $rD, $src", LdStLHA,
|
||||
"lwax $rD, $src", IIC_LdStLHA,
|
||||
[(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
|
||||
PPC970_DGroup_Cracked;
|
||||
// For fast-isel:
|
||||
let isCodeGenOnly = 1, mayLoad = 1 in {
|
||||
def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src),
|
||||
"lwa $rD, $src", LdStLWA, []>, isPPC64,
|
||||
"lwa $rD, $src", IIC_LdStLWA, []>, isPPC64,
|
||||
PPC970_DGroup_Cracked;
|
||||
def LWAX_32 : XForm_1<31, 341, (outs gprc:$rD), (ins memrr:$src),
|
||||
"lwax $rD, $src", LdStLHA, []>, isPPC64,
|
||||
"lwax $rD, $src", IIC_LdStLHA, []>, isPPC64,
|
||||
PPC970_DGroup_Cracked;
|
||||
} // end fast-isel isCodeGenOnly
|
||||
|
||||
@@ -652,7 +657,7 @@ let mayLoad = 1, neverHasSideEffects = 1 in {
|
||||
let Interpretation64Bit = 1 in
|
||||
def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
|
||||
(ins memri:$addr),
|
||||
"lhau $rD, $addr", LdStLHAU,
|
||||
"lhau $rD, $addr", IIC_LdStLHAU,
|
||||
[]>, RegConstraint<"$addr.reg = $ea_result">,
|
||||
NoEncode<"$ea_result">;
|
||||
// NO LWAU!
|
||||
@@ -660,12 +665,12 @@ def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
|
||||
let Interpretation64Bit = 1 in
|
||||
def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
|
||||
(ins memrr:$addr),
|
||||
"lhaux $rD, $addr", LdStLHAU,
|
||||
"lhaux $rD, $addr", IIC_LdStLHAU,
|
||||
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
|
||||
NoEncode<"$ea_result">;
|
||||
def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
|
||||
(ins memrr:$addr),
|
||||
"lwaux $rD, $addr", LdStLHAU,
|
||||
"lwaux $rD, $addr", IIC_LdStLHAU,
|
||||
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
|
||||
NoEncode<"$ea_result">, isPPC64;
|
||||
}
|
||||
@@ -675,54 +680,54 @@ let Interpretation64Bit = 1 in {
|
||||
// Zero extending loads.
|
||||
let canFoldAsLoad = 1, PPC970_Unit = 2 in {
|
||||
def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src),
|
||||
"lbz $rD, $src", LdStLoad,
|
||||
"lbz $rD, $src", IIC_LdStLoad,
|
||||
[(set i64:$rD, (zextloadi8 iaddr:$src))]>;
|
||||
def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src),
|
||||
"lhz $rD, $src", LdStLoad,
|
||||
"lhz $rD, $src", IIC_LdStLoad,
|
||||
[(set i64:$rD, (zextloadi16 iaddr:$src))]>;
|
||||
def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src),
|
||||
"lwz $rD, $src", LdStLoad,
|
||||
"lwz $rD, $src", IIC_LdStLoad,
|
||||
[(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
|
||||
|
||||
def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src),
|
||||
"lbzx $rD, $src", LdStLoad,
|
||||
"lbzx $rD, $src", IIC_LdStLoad,
|
||||
[(set i64:$rD, (zextloadi8 xaddr:$src))]>;
|
||||
def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src),
|
||||
"lhzx $rD, $src", LdStLoad,
|
||||
"lhzx $rD, $src", IIC_LdStLoad,
|
||||
[(set i64:$rD, (zextloadi16 xaddr:$src))]>;
|
||||
def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src),
|
||||
"lwzx $rD, $src", LdStLoad,
|
||||
"lwzx $rD, $src", IIC_LdStLoad,
|
||||
[(set i64:$rD, (zextloadi32 xaddr:$src))]>;
|
||||
|
||||
|
||||
// Update forms.
|
||||
let mayLoad = 1, neverHasSideEffects = 1 in {
|
||||
def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
|
||||
"lbzu $rD, $addr", LdStLoadUpd,
|
||||
"lbzu $rD, $addr", IIC_LdStLoadUpd,
|
||||
[]>, RegConstraint<"$addr.reg = $ea_result">,
|
||||
NoEncode<"$ea_result">;
|
||||
def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
|
||||
"lhzu $rD, $addr", LdStLoadUpd,
|
||||
"lhzu $rD, $addr", IIC_LdStLoadUpd,
|
||||
[]>, RegConstraint<"$addr.reg = $ea_result">,
|
||||
NoEncode<"$ea_result">;
|
||||
def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
|
||||
"lwzu $rD, $addr", LdStLoadUpd,
|
||||
"lwzu $rD, $addr", IIC_LdStLoadUpd,
|
||||
[]>, RegConstraint<"$addr.reg = $ea_result">,
|
||||
NoEncode<"$ea_result">;
|
||||
|
||||
def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
|
||||
(ins memrr:$addr),
|
||||
"lbzux $rD, $addr", LdStLoadUpd,
|
||||
"lbzux $rD, $addr", IIC_LdStLoadUpd,
|
||||
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
|
||||
NoEncode<"$ea_result">;
|
||||
def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
|
||||
(ins memrr:$addr),
|
||||
"lhzux $rD, $addr", LdStLoadUpd,
|
||||
"lhzux $rD, $addr", IIC_LdStLoadUpd,
|
||||
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
|
||||
NoEncode<"$ea_result">;
|
||||
def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
|
||||
(ins memrr:$addr),
|
||||
"lwzux $rD, $addr", LdStLoadUpd,
|
||||
"lwzux $rD, $addr", IIC_LdStLoadUpd,
|
||||
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
|
||||
NoEncode<"$ea_result">;
|
||||
}
|
||||
@@ -733,7 +738,7 @@ def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
|
||||
// Full 8-byte loads.
|
||||
let canFoldAsLoad = 1, PPC970_Unit = 2 in {
|
||||
def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src),
|
||||
"ld $rD, $src", LdStLD,
|
||||
"ld $rD, $src", IIC_LdStLD,
|
||||
[(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
|
||||
// The following three definitions are selected for small code model only.
|
||||
// Otherwise, we need to create two instructions to form a 32-bit offset,
|
||||
@@ -754,30 +759,30 @@ def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
|
||||
let hasSideEffects = 1, isCodeGenOnly = 1 in {
|
||||
let RST = 2, DS = 2 in
|
||||
def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg),
|
||||
"ld 2, 8($reg)", LdStLD,
|
||||
"ld 2, 8($reg)", IIC_LdStLD,
|
||||
[(PPCload_toc i64:$reg)]>, isPPC64;
|
||||
|
||||
let RST = 2, DS = 10, RA = 1 in
|
||||
def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
|
||||
"ld 2, 40(1)", LdStLD,
|
||||
"ld 2, 40(1)", IIC_LdStLD,
|
||||
[(PPCtoc_restore)]>, isPPC64;
|
||||
}
|
||||
def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src),
|
||||
"ldx $rD, $src", LdStLD,
|
||||
"ldx $rD, $src", IIC_LdStLD,
|
||||
[(set i64:$rD, (load xaddr:$src))]>, isPPC64;
|
||||
def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src),
|
||||
"ldbrx $rD, $src", LdStLoad,
|
||||
"ldbrx $rD, $src", IIC_LdStLoad,
|
||||
[(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
|
||||
|
||||
let mayLoad = 1, neverHasSideEffects = 1 in {
|
||||
def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
|
||||
"ldu $rD, $addr", LdStLDU,
|
||||
"ldu $rD, $addr", IIC_LdStLDU,
|
||||
[]>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
|
||||
NoEncode<"$ea_result">;
|
||||
|
||||
def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
|
||||
(ins memrr:$addr),
|
||||
"ldux $rD, $addr", LdStLDU,
|
||||
"ldux $rD, $addr", IIC_LdStLDU,
|
||||
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
|
||||
NoEncode<"$ea_result">, isPPC64;
|
||||
}
|
||||
@@ -863,38 +868,38 @@ let PPC970_Unit = 2 in {
|
||||
let Interpretation64Bit = 1 in {
|
||||
// Truncating stores.
|
||||
def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src),
|
||||
"stb $rS, $src", LdStStore,
|
||||
"stb $rS, $src", IIC_LdStStore,
|
||||
[(truncstorei8 i64:$rS, iaddr:$src)]>;
|
||||
def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src),
|
||||
"sth $rS, $src", LdStStore,
|
||||
"sth $rS, $src", IIC_LdStStore,
|
||||
[(truncstorei16 i64:$rS, iaddr:$src)]>;
|
||||
def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src),
|
||||
"stw $rS, $src", LdStStore,
|
||||
"stw $rS, $src", IIC_LdStStore,
|
||||
[(truncstorei32 i64:$rS, iaddr:$src)]>;
|
||||
def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst),
|
||||
"stbx $rS, $dst", LdStStore,
|
||||
"stbx $rS, $dst", IIC_LdStStore,
|
||||
[(truncstorei8 i64:$rS, xaddr:$dst)]>,
|
||||
PPC970_DGroup_Cracked;
|
||||
def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst),
|
||||
"sthx $rS, $dst", LdStStore,
|
||||
"sthx $rS, $dst", IIC_LdStStore,
|
||||
[(truncstorei16 i64:$rS, xaddr:$dst)]>,
|
||||
PPC970_DGroup_Cracked;
|
||||
def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst),
|
||||
"stwx $rS, $dst", LdStStore,
|
||||
"stwx $rS, $dst", IIC_LdStStore,
|
||||
[(truncstorei32 i64:$rS, xaddr:$dst)]>,
|
||||
PPC970_DGroup_Cracked;
|
||||
} // Interpretation64Bit
|
||||
|
||||
// Normal 8-byte stores.
|
||||
def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst),
|
||||
"std $rS, $dst", LdStSTD,
|
||||
"std $rS, $dst", IIC_LdStSTD,
|
||||
[(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64;
|
||||
def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst),
|
||||
"stdx $rS, $dst", LdStSTD,
|
||||
"stdx $rS, $dst", IIC_LdStSTD,
|
||||
[(store i64:$rS, xaddr:$dst)]>, isPPC64,
|
||||
PPC970_DGroup_Cracked;
|
||||
def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
|
||||
"stdbrx $rS, $dst", LdStStore,
|
||||
"stdbrx $rS, $dst", IIC_LdStStore,
|
||||
[(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64,
|
||||
PPC970_DGroup_Cracked;
|
||||
}
|
||||
@@ -903,35 +908,35 @@ def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
|
||||
let PPC970_Unit = 2, mayStore = 1 in {
|
||||
let Interpretation64Bit = 1 in {
|
||||
def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
|
||||
"stbu $rS, $dst", LdStStoreUpd, []>,
|
||||
"stbu $rS, $dst", IIC_LdStStoreUpd, []>,
|
||||
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
|
||||
def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
|
||||
"sthu $rS, $dst", LdStStoreUpd, []>,
|
||||
"sthu $rS, $dst", IIC_LdStStoreUpd, []>,
|
||||
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
|
||||
def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
|
||||
"stwu $rS, $dst", LdStStoreUpd, []>,
|
||||
"stwu $rS, $dst", IIC_LdStStoreUpd, []>,
|
||||
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
|
||||
def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst),
|
||||
"stdu $rS, $dst", LdStSTDU, []>,
|
||||
"stdu $rS, $dst", IIC_LdStSTDU, []>,
|
||||
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
|
||||
isPPC64;
|
||||
|
||||
def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
|
||||
"stbux $rS, $dst", LdStStoreUpd, []>,
|
||||
"stbux $rS, $dst", IIC_LdStStoreUpd, []>,
|
||||
RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
|
||||
PPC970_DGroup_Cracked;
|
||||
def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
|
||||
"sthux $rS, $dst", LdStStoreUpd, []>,
|
||||
"sthux $rS, $dst", IIC_LdStStoreUpd, []>,
|
||||
RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
|
||||
PPC970_DGroup_Cracked;
|
||||
def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
|
||||
"stwux $rS, $dst", LdStStoreUpd, []>,
|
||||
"stwux $rS, $dst", IIC_LdStStoreUpd, []>,
|
||||
RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
|
||||
PPC970_DGroup_Cracked;
|
||||
} // Interpretation64Bit
|
||||
|
||||
def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
|
||||
"stdux $rS, $dst", LdStSTDU, []>,
|
||||
"stdux $rS, $dst", IIC_LdStSTDU, []>,
|
||||
RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
|
||||
PPC970_DGroup_Cracked, isPPC64;
|
||||
}
|
||||
@@ -966,29 +971,29 @@ def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
|
||||
let PPC970_Unit = 3, neverHasSideEffects = 1,
|
||||
Uses = [RM] in { // FPU Operations.
|
||||
defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),
|
||||
"fcfid", "$frD, $frB", FPGeneral,
|
||||
"fcfid", "$frD, $frB", IIC_FPGeneral,
|
||||
[(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
|
||||
defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB),
|
||||
"fctid", "$frD, $frB", FPGeneral,
|
||||
"fctid", "$frD, $frB", IIC_FPGeneral,
|
||||
[]>, isPPC64;
|
||||
defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
|
||||
"fctidz", "$frD, $frB", FPGeneral,
|
||||
"fctidz", "$frD, $frB", IIC_FPGeneral,
|
||||
[(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
|
||||
|
||||
defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB),
|
||||
"fcfidu", "$frD, $frB", FPGeneral,
|
||||
"fcfidu", "$frD, $frB", IIC_FPGeneral,
|
||||
[(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64;
|
||||
defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB),
|
||||
"fcfids", "$frD, $frB", FPGeneral,
|
||||
"fcfids", "$frD, $frB", IIC_FPGeneral,
|
||||
[(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64;
|
||||
defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB),
|
||||
"fcfidus", "$frD, $frB", FPGeneral,
|
||||
"fcfidus", "$frD, $frB", IIC_FPGeneral,
|
||||
[(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64;
|
||||
defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB),
|
||||
"fctiduz", "$frD, $frB", FPGeneral,
|
||||
"fctiduz", "$frD, $frB", IIC_FPGeneral,
|
||||
[(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64;
|
||||
defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB),
|
||||
"fctiwuz", "$frD, $frB", FPGeneral,
|
||||
"fctiwuz", "$frD, $frB", IIC_FPGeneral,
|
||||
[(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64;
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user