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Add IIC_ prefix to PPC instruction-class names

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This adds the IIC_ prefix to the instruction itinerary class names, giving the
PPC backend a naming convention for itinerary classes that is more consistent
with that used by the X86 and ARM backends.

Instruction scheduling in the PPC backend needs a bunch of cleanup and
improvement (especially for the ooo cores). This is just a preliminary step.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195890 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel
2013-11-27 23:26:09 +00:00
parent fe7d0c3534
commit d99338105b
13 changed files with 2366 additions and 2355 deletions
Download Patch File Download Diff File Expand all files Collapse all files

293
lib/Target/PowerPC/PPCInstr64Bit.td
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@@ -83,12 +83,14 @@ def HI48_64 : SDNodeXForm<imm, [{
let Interpretation64Bit = 1 in { let Interpretation64Bit = 1 in {
let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
[]>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
let isCodeGenOnly = 1 in let isCodeGenOnly = 1 in
def BCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), def BCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
"b${cond:cc}ctr${cond:pm} ${cond:reg}", BrB, []>, "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
[]>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
} }
} }
@@ -107,9 +109,9 @@ let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
"bdzlr", BrB, []>; "bdzlr", IIC_BrB, []>;
def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
"bdnzlr", BrB, []>; "bdnzlr", IIC_BrB, []>;
} }
} }
@@ -119,36 +121,37 @@ let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
// Convenient aliases for call instructions // Convenient aliases for call instructions
let Uses = [RM] in { let Uses = [RM] in {
def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
"bl $func", BrB, []>; // See Pat patterns below. "bl $func", IIC_BrB, []>; // See Pat patterns below.
def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func),
"bl $func", BrB, []>; "bl $func", IIC_BrB, []>;
def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
"bla $func", BrB, [(PPCcall (i64 imm:$func))]>; "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>;
} }
let Uses = [RM], isCodeGenOnly = 1 in { let Uses = [RM], isCodeGenOnly = 1 in {
def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
(outs), (ins calltarget:$func), (outs), (ins calltarget:$func),
"bl $func\n\tnop", BrB, []>; "bl $func\n\tnop", IIC_BrB, []>;
def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24,
(outs), (ins tlscall:$func), (outs), (ins tlscall:$func),
"bl $func\n\tnop", BrB, []>; "bl $func\n\tnop", IIC_BrB, []>;
def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
(outs), (ins abscalltarget:$func), (outs), (ins abscalltarget:$func),
"bla $func\n\tnop", BrB, "bla $func\n\tnop", IIC_BrB,
[(PPCcall_nop (i64 imm:$func))]>; [(PPCcall_nop (i64 imm:$func))]>;
} }
let Uses = [CTR8, RM] in { let Uses = [CTR8, RM] in {
def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
"bctrl", BrB, [(PPCbctrl)]>, "bctrl", IIC_BrB, [(PPCbctrl)]>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
let isCodeGenOnly = 1 in let isCodeGenOnly = 1 in
def BCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), def BCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
"b${cond:cc}ctrl${cond:pm} ${cond:reg}", BrB, []>, "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
[]>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
} }
} }
@@ -199,12 +202,12 @@ let usesCustomInserter = 1 in {
// Instructions to support atomic operations // Instructions to support atomic operations
def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
"ldarx $rD, $ptr", LdStLDARX, "ldarx $rD, $ptr", IIC_LdStLDARX,
[(set i64:$rD, (PPClarx xoaddr:$ptr))]>; [(set i64:$rD, (PPClarx xoaddr:$ptr))]>;
let Defs = [CR0] in let Defs = [CR0] in
def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
"stdcx. $rS, $dst", LdStSTDCX, "stdcx. $rS, $dst", IIC_LdStSTDCX,
[(PPCstcx i64:$rS, xoaddr:$dst)]>, [(PPCstcx i64:$rS, xoaddr:$dst)]>,
isDOT; isDOT;
@@ -229,21 +232,22 @@ let isCodeGenOnly = 1 in {
let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
[]>,
Requires<[In64BitMode]>; Requires<[In64BitMode]>;
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
"b $dst", BrB, "b $dst", IIC_BrB,
[]>; []>;
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
"ba $dst", BrB, "ba $dst", IIC_BrB,
[]>; []>;
} }
@@ -263,20 +267,20 @@ def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
let Interpretation64Bit = 1 in { let Interpretation64Bit = 1 in {
let neverHasSideEffects = 1 in { let neverHasSideEffects = 1 in {
def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST), def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST),
"mtocrf $FXM, $ST", BrMCRX>, "mtocrf $FXM, $ST", IIC_BrMCRX>,
PPC970_DGroup_First, PPC970_Unit_CRU; PPC970_DGroup_First, PPC970_Unit_CRU;
def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS), def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS),
"mtcrf $FXM, $rS", BrMCRX>, "mtcrf $FXM, $rS", IIC_BrMCRX>,
PPC970_MicroCode, PPC970_Unit_CRU; PPC970_MicroCode, PPC970_Unit_CRU;
let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking. let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM),
"mfocrf $rT, $FXM", SprMFCR>, "mfocrf $rT, $FXM", IIC_SprMFCR>,
PPC970_DGroup_First, PPC970_Unit_CRU; PPC970_DGroup_First, PPC970_Unit_CRU;
def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins),
"mfcr $rT", SprMFCR>, "mfcr $rT", IIC_SprMFCR>,
PPC970_MicroCode, PPC970_Unit_CRU; PPC970_MicroCode, PPC970_Unit_CRU;
} // neverHasSideEffects = 1 } // neverHasSideEffects = 1
@@ -298,24 +302,24 @@ let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
let Uses = [CTR8] in { let Uses = [CTR8] in {
def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins),
"mfctr $rT", SprMFSPR>, "mfctr $rT", IIC_SprMFSPR>,
PPC970_DGroup_First, PPC970_Unit_FXU; PPC970_DGroup_First, PPC970_Unit_FXU;
} }
let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in {
def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
"mtctr $rS", SprMTSPR>, "mtctr $rS", IIC_SprMTSPR>,
PPC970_DGroup_First, PPC970_Unit_FXU; PPC970_DGroup_First, PPC970_Unit_FXU;
} }
let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR8] in { let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR8] in {
let Pattern = [(int_ppc_mtctr i64:$rS)] in let Pattern = [(int_ppc_mtctr i64:$rS)] in
def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
"mtctr $rS", SprMTSPR>, "mtctr $rS", IIC_SprMTSPR>,
PPC970_DGroup_First, PPC970_Unit_FXU; PPC970_DGroup_First, PPC970_Unit_FXU;
} }
let isCodeGenOnly = 1, Pattern = [(set i64:$rT, readcyclecounter)] in let isCodeGenOnly = 1, Pattern = [(set i64:$rT, readcyclecounter)] in
def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins),
"mfspr $rT, 268", SprMFTB>, "mfspr $rT, 268", IIC_SprMFTB>,
PPC970_DGroup_First, PPC970_Unit_FXU; PPC970_DGroup_First, PPC970_Unit_FXU;
// Note that encoding mftb using mfspr is now the preferred form, // Note that encoding mftb using mfspr is now the preferred form,
// and has been since at least ISA v2.03. The mftb instruction has // and has been since at least ISA v2.03. The mftb instruction has
@@ -329,12 +333,12 @@ def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#D
let Defs = [LR8] in { let Defs = [LR8] in {
def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS),
"mtlr $rS", SprMTSPR>, "mtlr $rS", IIC_SprMTSPR>,
PPC970_DGroup_First, PPC970_Unit_FXU; PPC970_DGroup_First, PPC970_Unit_FXU;
} }
let Uses = [LR8] in { let Uses = [LR8] in {
def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins),
"mflr $rT", SprMFSPR>, "mflr $rT", IIC_SprMFSPR>,
PPC970_DGroup_First, PPC970_Unit_FXU; PPC970_DGroup_First, PPC970_Unit_FXU;
} }
} // Interpretation64Bit } // Interpretation64Bit
@@ -349,210 +353,211 @@ let neverHasSideEffects = 1 in {
let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm),
"li $rD, $imm", IntSimple, "li $rD, $imm", IIC_IntSimple,
[(set i64:$rD, imm64SExt16:$imm)]>; [(set i64:$rD, imm64SExt16:$imm)]>;
def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm),
"lis $rD, $imm", IntSimple, "lis $rD, $imm", IIC_IntSimple,
[(set i64:$rD, imm16ShiftedSExt:$imm)]>; [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
} }
// Logical ops. // Logical ops.
defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
"nand", "$rA, $rS, $rB", IntSimple, "nand", "$rA, $rS, $rB", IIC_IntSimple,
[(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
"and", "$rA, $rS, $rB", IntSimple, "and", "$rA, $rS, $rB", IIC_IntSimple,
[(set i64:$rA, (and i64:$rS, i64:$rB))]>; [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
"andc", "$rA, $rS, $rB", IntSimple, "andc", "$rA, $rS, $rB", IIC_IntSimple,
[(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>;
defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
"or", "$rA, $rS, $rB", IntSimple, "or", "$rA, $rS, $rB", IIC_IntSimple,
[(set i64:$rA, (or i64:$rS, i64:$rB))]>; [(set i64:$rA, (or i64:$rS, i64:$rB))]>;
defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
"nor", "$rA, $rS, $rB", IntSimple, "nor", "$rA, $rS, $rB", IIC_IntSimple,
[(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>;
defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
"orc", "$rA, $rS, $rB", IntSimple, "orc", "$rA, $rS, $rB", IIC_IntSimple,
[(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>;
defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
"eqv", "$rA, $rS, $rB", IntSimple, "eqv", "$rA, $rS, $rB", IIC_IntSimple,
[(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
"xor", "$rA, $rS, $rB", IntSimple, "xor", "$rA, $rS, $rB", IIC_IntSimple,
[(set i64:$rA, (xor i64:$rS, i64:$rB))]>; [(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
// Logical ops with immediate. // Logical ops with immediate.
let Defs = [CR0] in { let Defs = [CR0] in {
def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
"andi. $dst, $src1, $src2", IntGeneral, "andi. $dst, $src1, $src2", IIC_IntGeneral,
[(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
isDOT; isDOT;
def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
"andis. $dst, $src1, $src2", IntGeneral, "andis. $dst, $src1, $src2", IIC_IntGeneral,
[(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
isDOT; isDOT;
} }
def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
"ori $dst, $src1, $src2", IntSimple, "ori $dst, $src1, $src2", IIC_IntSimple,
[(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
"oris $dst, $src1, $src2", IntSimple, "oris $dst, $src1, $src2", IIC_IntSimple,
[(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
"xori $dst, $src1, $src2", IntSimple, "xori $dst, $src1, $src2", IIC_IntSimple,
[(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>;
def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
"xoris $dst, $src1, $src2", IntSimple, "xoris $dst, $src1, $src2", IIC_IntSimple,
[(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>;
defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
"add", "$rT, $rA, $rB", IntSimple, "add", "$rT, $rA, $rB", IIC_IntSimple,
[(set i64:$rT, (add i64:$rA, i64:$rB))]>; [(set i64:$rT, (add i64:$rA, i64:$rB))]>;
// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
// initial-exec thread-local storage model. // initial-exec thread-local storage model.
def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
"add $rT, $rA, $rB", IntSimple, "add $rT, $rA, $rB", IIC_IntSimple,
[(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>;
defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
"addc", "$rT, $rA, $rB", IntGeneral, "addc", "$rT, $rA, $rB", IIC_IntGeneral,
[(set i64:$rT, (addc i64:$rA, i64:$rB))]>, [(set i64:$rT, (addc i64:$rA, i64:$rB))]>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
let Defs = [CARRY] in let Defs = [CARRY] in
def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
"addic $rD, $rA, $imm", IntGeneral, "addic $rD, $rA, $imm", IIC_IntGeneral,
[(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>;
def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm),
"addi $rD, $rA, $imm", IntSimple, "addi $rD, $rA, $imm", IIC_IntSimple,
[(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>;
def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm),
"addis $rD, $rA, $imm", IntSimple, "addis $rD, $rA, $imm", IIC_IntSimple,
[(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>;
let Defs = [CARRY] in { let Defs = [CARRY] in {
def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
"subfic $rD, $rA, $imm", IntGeneral, "subfic $rD, $rA, $imm", IIC_IntGeneral,
[(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>;
defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
"subfc", "$rT, $rA, $rB", IntGeneral, "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
[(set i64:$rT, (subc i64:$rB, i64:$rA))]>, [(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
} }
defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
"subf", "$rT, $rA, $rB", IntGeneral, "subf", "$rT, $rA, $rB", IIC_IntGeneral,
[(set i64:$rT, (sub i64:$rB, i64:$rA))]>; [(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA),
"neg", "$rT, $rA", IntSimple, "neg", "$rT, $rA", IIC_IntSimple,
[(set i64:$rT, (ineg i64:$rA))]>; [(set i64:$rT, (ineg i64:$rA))]>;
let Uses = [CARRY] in { let Uses = [CARRY] in {
defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
"adde", "$rT, $rA, $rB", IntGeneral, "adde", "$rT, $rA, $rB", IIC_IntGeneral,
[(set i64:$rT, (adde i64:$rA, i64:$rB))]>; [(set i64:$rT, (adde i64:$rA, i64:$rB))]>;
defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA),
"addme", "$rT, $rA", IntGeneral, "addme", "$rT, $rA", IIC_IntGeneral,
[(set i64:$rT, (adde i64:$rA, -1))]>; [(set i64:$rT, (adde i64:$rA, -1))]>;
defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA),
"addze", "$rT, $rA", IntGeneral, "addze", "$rT, $rA", IIC_IntGeneral,
[(set i64:$rT, (adde i64:$rA, 0))]>; [(set i64:$rT, (adde i64:$rA, 0))]>;
defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
"subfe", "$rT, $rA, $rB", IntGeneral, "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
[(set i64:$rT, (sube i64:$rB, i64:$rA))]>; [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA),
"subfme", "$rT, $rA", IntGeneral, "subfme", "$rT, $rA", IIC_IntGeneral,
[(set i64:$rT, (sube -1, i64:$rA))]>; [(set i64:$rT, (sube -1, i64:$rA))]>;
defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA),
"subfze", "$rT, $rA", IntGeneral, "subfze", "$rT, $rA", IIC_IntGeneral,
[(set i64:$rT, (sube 0, i64:$rA))]>; [(set i64:$rT, (sube 0, i64:$rA))]>;
} }
defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
"mulhd", "$rT, $rA, $rB", IntMulHW, "mulhd", "$rT, $rA, $rB", IIC_IntMulHW,
[(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
"mulhdu", "$rT, $rA, $rB", IntMulHWU, "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU,
[(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
} }
} // Interpretation64Bit } // Interpretation64Bit
let isCompare = 1, neverHasSideEffects = 1 in { let isCompare = 1, neverHasSideEffects = 1 in {
def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
"cmpd $crD, $rA, $rB", IntCompare>, isPPC64; "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64;
def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
"cmpld $crD, $rA, $rB", IntCompare>, isPPC64; "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64;
def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm:$imm), def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm:$imm),
"cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64;
def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm:$src2), def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm:$src2),
"cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; "cmpldi $dst, $src1, $src2",
IIC_IntCompare>, isPPC64;
} }
let neverHasSideEffects = 1 in { let neverHasSideEffects = 1 in {
defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
"sld", "$rA, $rS, $rB", IntRotateD, "sld", "$rA, $rS, $rB", IIC_IntRotateD,
[(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64;
defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
"srd", "$rA, $rS, $rB", IntRotateD, "srd", "$rA, $rS, $rB", IIC_IntRotateD,
[(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64;
defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
"srad", "$rA, $rS, $rB", IntRotateD, "srad", "$rA, $rS, $rB", IIC_IntRotateD,
[(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64;
let Interpretation64Bit = 1 in { let Interpretation64Bit = 1 in {
defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS),
"extsb", "$rA, $rS", IntSimple, "extsb", "$rA, $rS", IIC_IntSimple,
[(set i64:$rA, (sext_inreg i64:$rS, i8))]>; [(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS),
"extsh", "$rA, $rS", IntSimple, "extsh", "$rA, $rS", IIC_IntSimple,
[(set i64:$rA, (sext_inreg i64:$rS, i16))]>; [(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
} // Interpretation64Bit } // Interpretation64Bit
// For fast-isel: // For fast-isel:
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS), def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS),
"extsb $rA, $rS", IntSimple, []>, isPPC64; "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64;
def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS), def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS),
"extsh $rA, $rS", IntSimple, []>, isPPC64; "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64;
} // isCodeGenOnly for fast-isel } // isCodeGenOnly for fast-isel
defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS),
"extsw", "$rA, $rS", IntSimple, "extsw", "$rA, $rS", IIC_IntSimple,
[(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
let Interpretation64Bit = 1 in let Interpretation64Bit = 1 in
defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
"extsw", "$rA, $rS", IntSimple, "extsw", "$rA, $rS", IIC_IntSimple,
[(set i64:$rA, (sext i32:$rS))]>, isPPC64; [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
"sradi", "$rA, $rS, $SH", IntRotateDI, "sradi", "$rA, $rS, $SH", IIC_IntRotateDI,
[(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
"cntlzd", "$rA, $rS", IntGeneral, "cntlzd", "$rA, $rS", IIC_IntGeneral,
[(set i64:$rA, (ctlz i64:$rS))]>; [(set i64:$rA, (ctlz i64:$rS))]>;
def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
"popcntd $rA, $rS", IntGeneral, "popcntd $rA, $rS", IIC_IntGeneral,
[(set i64:$rA, (ctpop i64:$rS))]>; [(set i64:$rA, (ctpop i64:$rS))]>;
// popcntw also does a population count on the high 32 bits (storing the // popcntw also does a population count on the high 32 bits (storing the
// results in the high 32-bits of the output). We'll ignore that here (which is // results in the high 32-bits of the output). We'll ignore that here (which is
// safe because we never separately use the high part of the 64-bit registers). // safe because we never separately use the high part of the 64-bit registers).
def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS), def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS),
"popcntw $rA, $rS", IntGeneral, "popcntw $rA, $rS", IIC_IntGeneral,
[(set i32:$rA, (ctpop i32:$rS))]>; [(set i32:$rA, (ctpop i32:$rS))]>;
defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
"divd", "$rT, $rA, $rB", IntDivD, "divd", "$rT, $rA, $rB", IIC_IntDivD,
[(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64, [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64,
PPC970_DGroup_First, PPC970_DGroup_Cracked; PPC970_DGroup_First, PPC970_DGroup_Cracked;
defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
"divdu", "$rT, $rA, $rB", IntDivD, "divdu", "$rT, $rA, $rB", IIC_IntDivD,
[(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64, [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64,
PPC970_DGroup_First, PPC970_DGroup_Cracked; PPC970_DGroup_First, PPC970_DGroup_Cracked;
defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
"mulld", "$rT, $rA, $rB", IntMulHD, "mulld", "$rT, $rA, $rB", IIC_IntMulHD,
[(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
"mulli $rD, $rA, $imm", IntMulLI, "mulli $rD, $rA, $imm", IIC_IntMulLI,
[(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>; [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>;
} }
@@ -560,7 +565,7 @@ let neverHasSideEffects = 1 in {
let isCommutable = 1 in { let isCommutable = 1 in {
defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA),
(ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE),
"rldimi", "$rA, $rS, $SH, $MBE", IntRotateDI, "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
[]>, isPPC64, RegConstraint<"$rSi = $rA">, []>, isPPC64, RegConstraint<"$rSi = $rA">,
NoEncode<"$rSi">; NoEncode<"$rSi">;
} }
@@ -568,43 +573,43 @@ defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA),
// Rotate instructions. // Rotate instructions.
defm RLDCL : MDSForm_1r<30, 8, defm RLDCL : MDSForm_1r<30, 8,
(outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
"rldcl", "$rA, $rS, $rB, $MBE", IntRotateD, "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD,
[]>, isPPC64; []>, isPPC64;
defm RLDCR : MDSForm_1r<30, 9, defm RLDCR : MDSForm_1r<30, 9,
(outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
"rldcr", "$rA, $rS, $rB, $MBE", IntRotateD, "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD,
[]>, isPPC64; []>, isPPC64;
defm RLDICL : MDForm_1r<30, 0, defm RLDICL : MDForm_1r<30, 0,
(outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
"rldicl", "$rA, $rS, $SH, $MBE", IntRotateDI, "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
[]>, isPPC64; []>, isPPC64;
// For fast-isel: // For fast-isel:
let isCodeGenOnly = 1 in let isCodeGenOnly = 1 in
def RLDICL_32_64 : MDForm_1<30, 0, def RLDICL_32_64 : MDForm_1<30, 0,
(outs g8rc:$rA), (outs g8rc:$rA),
(ins gprc:$rS, u6imm:$SH, u6imm:$MBE), (ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
"rldicl $rA, $rS, $SH, $MBE", IntRotateDI, "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI,
[]>, isPPC64; []>, isPPC64;
// End fast-isel. // End fast-isel.
defm RLDICR : MDForm_1r<30, 1, defm RLDICR : MDForm_1r<30, 1,
(outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
"rldicr", "$rA, $rS, $SH, $MBE", IntRotateDI, "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
[]>, isPPC64; []>, isPPC64;
defm RLDIC : MDForm_1r<30, 2, defm RLDIC : MDForm_1r<30, 2,
(outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
"rldic", "$rA, $rS, $SH, $MBE", IntRotateDI, "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
[]>, isPPC64; []>, isPPC64;
let Interpretation64Bit = 1 in { let Interpretation64Bit = 1 in {
defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA),
(ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
"rlwinm", "$rA, $rS, $SH, $MB, $ME", IntGeneral, "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
[]>; []>;
let isSelect = 1 in let isSelect = 1 in
def ISEL8 : AForm_4<31, 15, def ISEL8 : AForm_4<31, 15,
(outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond),
"isel $rT, $rA, $rB, $cond", IntGeneral, "isel $rT, $rA, $rB, $cond", IIC_IntGeneral,
[]>; []>;
} // Interpretation64Bit } // Interpretation64Bit
} // neverHasSideEffects = 1 } // neverHasSideEffects = 1
@@ -620,30 +625,30 @@ def ISEL8 : AForm_4<31, 15,
let canFoldAsLoad = 1, PPC970_Unit = 2 in { let canFoldAsLoad = 1, PPC970_Unit = 2 in {
let Interpretation64Bit = 1 in let Interpretation64Bit = 1 in
def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src),
"lha $rD, $src", LdStLHA, "lha $rD, $src", IIC_LdStLHA,
[(set i64:$rD, (sextloadi16 iaddr:$src))]>, [(set i64:$rD, (sextloadi16 iaddr:$src))]>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src),
"lwa $rD, $src", LdStLWA, "lwa $rD, $src", IIC_LdStLWA,
[(set i64:$rD, [(set i64:$rD,
(aligned4sextloadi32 ixaddr:$src))]>, isPPC64, (aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
let Interpretation64Bit = 1 in let Interpretation64Bit = 1 in
def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src), def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src),
"lhax $rD, $src", LdStLHA, "lhax $rD, $src", IIC_LdStLHA,
[(set i64:$rD, (sextloadi16 xaddr:$src))]>, [(set i64:$rD, (sextloadi16 xaddr:$src))]>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src), def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src),
"lwax $rD, $src", LdStLHA, "lwax $rD, $src", IIC_LdStLHA,
[(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
// For fast-isel: // For fast-isel:
let isCodeGenOnly = 1, mayLoad = 1 in { let isCodeGenOnly = 1, mayLoad = 1 in {
def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src), def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src),
"lwa $rD, $src", LdStLWA, []>, isPPC64, "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def LWAX_32 : XForm_1<31, 341, (outs gprc:$rD), (ins memrr:$src), def LWAX_32 : XForm_1<31, 341, (outs gprc:$rD), (ins memrr:$src),
"lwax $rD, $src", LdStLHA, []>, isPPC64, "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
} // end fast-isel isCodeGenOnly } // end fast-isel isCodeGenOnly
@@ -652,7 +657,7 @@ let mayLoad = 1, neverHasSideEffects = 1 in {
let Interpretation64Bit = 1 in let Interpretation64Bit = 1 in
def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
(ins memri:$addr), (ins memri:$addr),
"lhau $rD, $addr", LdStLHAU, "lhau $rD, $addr", IIC_LdStLHAU,
[]>, RegConstraint<"$addr.reg = $ea_result">, []>, RegConstraint<"$addr.reg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
// NO LWAU! // NO LWAU!
@@ -660,12 +665,12 @@ def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
let Interpretation64Bit = 1 in let Interpretation64Bit = 1 in
def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
(ins memrr:$addr), (ins memrr:$addr),
"lhaux $rD, $addr", LdStLHAU, "lhaux $rD, $addr", IIC_LdStLHAU,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">, []>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
(ins memrr:$addr), (ins memrr:$addr),
"lwaux $rD, $addr", LdStLHAU, "lwaux $rD, $addr", IIC_LdStLHAU,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">, []>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">, isPPC64; NoEncode<"$ea_result">, isPPC64;
} }
@@ -675,54 +680,54 @@ let Interpretation64Bit = 1 in {
// Zero extending loads. // Zero extending loads.
let canFoldAsLoad = 1, PPC970_Unit = 2 in { let canFoldAsLoad = 1, PPC970_Unit = 2 in {
def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src),
"lbz $rD, $src", LdStLoad, "lbz $rD, $src", IIC_LdStLoad,
[(set i64:$rD, (zextloadi8 iaddr:$src))]>; [(set i64:$rD, (zextloadi8 iaddr:$src))]>;
def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src),
"lhz $rD, $src", LdStLoad, "lhz $rD, $src", IIC_LdStLoad,
[(set i64:$rD, (zextloadi16 iaddr:$src))]>; [(set i64:$rD, (zextloadi16 iaddr:$src))]>;
def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src),
"lwz $rD, $src", LdStLoad, "lwz $rD, $src", IIC_LdStLoad,
[(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src), def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src),
"lbzx $rD, $src", LdStLoad, "lbzx $rD, $src", IIC_LdStLoad,
[(set i64:$rD, (zextloadi8 xaddr:$src))]>; [(set i64:$rD, (zextloadi8 xaddr:$src))]>;
def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src), def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src),
"lhzx $rD, $src", LdStLoad, "lhzx $rD, $src", IIC_LdStLoad,
[(set i64:$rD, (zextloadi16 xaddr:$src))]>; [(set i64:$rD, (zextloadi16 xaddr:$src))]>;
def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src), def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src),
"lwzx $rD, $src", LdStLoad, "lwzx $rD, $src", IIC_LdStLoad,
[(set i64:$rD, (zextloadi32 xaddr:$src))]>; [(set i64:$rD, (zextloadi32 xaddr:$src))]>;
// Update forms. // Update forms.
let mayLoad = 1, neverHasSideEffects = 1 in { let mayLoad = 1, neverHasSideEffects = 1 in {
def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
"lbzu $rD, $addr", LdStLoadUpd, "lbzu $rD, $addr", IIC_LdStLoadUpd,
[]>, RegConstraint<"$addr.reg = $ea_result">, []>, RegConstraint<"$addr.reg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
"lhzu $rD, $addr", LdStLoadUpd, "lhzu $rD, $addr", IIC_LdStLoadUpd,
[]>, RegConstraint<"$addr.reg = $ea_result">, []>, RegConstraint<"$addr.reg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
"lwzu $rD, $addr", LdStLoadUpd, "lwzu $rD, $addr", IIC_LdStLoadUpd,
[]>, RegConstraint<"$addr.reg = $ea_result">, []>, RegConstraint<"$addr.reg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
(ins memrr:$addr), (ins memrr:$addr),
"lbzux $rD, $addr", LdStLoadUpd, "lbzux $rD, $addr", IIC_LdStLoadUpd,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">, []>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
(ins memrr:$addr), (ins memrr:$addr),
"lhzux $rD, $addr", LdStLoadUpd, "lhzux $rD, $addr", IIC_LdStLoadUpd,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">, []>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
(ins memrr:$addr), (ins memrr:$addr),
"lwzux $rD, $addr", LdStLoadUpd, "lwzux $rD, $addr", IIC_LdStLoadUpd,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">, []>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
} }
@@ -733,7 +738,7 @@ def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
// Full 8-byte loads. // Full 8-byte loads.
let canFoldAsLoad = 1, PPC970_Unit = 2 in { let canFoldAsLoad = 1, PPC970_Unit = 2 in {
def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src),
"ld $rD, $src", LdStLD, "ld $rD, $src", IIC_LdStLD,
[(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64; [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
// The following three definitions are selected for small code model only. // The following three definitions are selected for small code model only.
// Otherwise, we need to create two instructions to form a 32-bit offset, // Otherwise, we need to create two instructions to form a 32-bit offset,
@@ -754,30 +759,30 @@ def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
let hasSideEffects = 1, isCodeGenOnly = 1 in { let hasSideEffects = 1, isCodeGenOnly = 1 in {
let RST = 2, DS = 2 in let RST = 2, DS = 2 in
def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg), def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg),
"ld 2, 8($reg)", LdStLD, "ld 2, 8($reg)", IIC_LdStLD,
[(PPCload_toc i64:$reg)]>, isPPC64; [(PPCload_toc i64:$reg)]>, isPPC64;
let RST = 2, DS = 10, RA = 1 in let RST = 2, DS = 10, RA = 1 in
def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins), def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
"ld 2, 40(1)", LdStLD, "ld 2, 40(1)", IIC_LdStLD,
[(PPCtoc_restore)]>, isPPC64; [(PPCtoc_restore)]>, isPPC64;
} }
def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src), def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src),
"ldx $rD, $src", LdStLD, "ldx $rD, $src", IIC_LdStLD,
[(set i64:$rD, (load xaddr:$src))]>, isPPC64; [(set i64:$rD, (load xaddr:$src))]>, isPPC64;
def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src), def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src),
"ldbrx $rD, $src", LdStLoad, "ldbrx $rD, $src", IIC_LdStLoad,
[(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64; [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
let mayLoad = 1, neverHasSideEffects = 1 in { let mayLoad = 1, neverHasSideEffects = 1 in {
def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr), def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
"ldu $rD, $addr", LdStLDU, "ldu $rD, $addr", IIC_LdStLDU,
[]>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
NoEncode<"$ea_result">; NoEncode<"$ea_result">;
def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
(ins memrr:$addr), (ins memrr:$addr),
"ldux $rD, $addr", LdStLDU, "ldux $rD, $addr", IIC_LdStLDU,
[]>, RegConstraint<"$addr.ptrreg = $ea_result">, []>, RegConstraint<"$addr.ptrreg = $ea_result">,
NoEncode<"$ea_result">, isPPC64; NoEncode<"$ea_result">, isPPC64;
} }
@@ -863,38 +868,38 @@ let PPC970_Unit = 2 in {
let Interpretation64Bit = 1 in { let Interpretation64Bit = 1 in {
// Truncating stores. // Truncating stores.
def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src),
"stb $rS, $src", LdStStore, "stb $rS, $src", IIC_LdStStore,
[(truncstorei8 i64:$rS, iaddr:$src)]>; [(truncstorei8 i64:$rS, iaddr:$src)]>;
def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src),
"sth $rS, $src", LdStStore, "sth $rS, $src", IIC_LdStStore,
[(truncstorei16 i64:$rS, iaddr:$src)]>; [(truncstorei16 i64:$rS, iaddr:$src)]>;
def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src),
"stw $rS, $src", LdStStore, "stw $rS, $src", IIC_LdStStore,
[(truncstorei32 i64:$rS, iaddr:$src)]>; [(truncstorei32 i64:$rS, iaddr:$src)]>;
def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst),
"stbx $rS, $dst", LdStStore, "stbx $rS, $dst", IIC_LdStStore,
[(truncstorei8 i64:$rS, xaddr:$dst)]>, [(truncstorei8 i64:$rS, xaddr:$dst)]>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst),
"sthx $rS, $dst", LdStStore, "sthx $rS, $dst", IIC_LdStStore,
[(truncstorei16 i64:$rS, xaddr:$dst)]>, [(truncstorei16 i64:$rS, xaddr:$dst)]>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst),
"stwx $rS, $dst", LdStStore, "stwx $rS, $dst", IIC_LdStStore,
[(truncstorei32 i64:$rS, xaddr:$dst)]>, [(truncstorei32 i64:$rS, xaddr:$dst)]>,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
} // Interpretation64Bit } // Interpretation64Bit
// Normal 8-byte stores. // Normal 8-byte stores.
def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst),
"std $rS, $dst", LdStSTD, "std $rS, $dst", IIC_LdStSTD,
[(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64; [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64;
def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst),
"stdx $rS, $dst", LdStSTD, "stdx $rS, $dst", IIC_LdStSTD,
[(store i64:$rS, xaddr:$dst)]>, isPPC64, [(store i64:$rS, xaddr:$dst)]>, isPPC64,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
"stdbrx $rS, $dst", LdStStore, "stdbrx $rS, $dst", IIC_LdStStore,
[(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64, [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
} }
@@ -903,35 +908,35 @@ def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
let PPC970_Unit = 2, mayStore = 1 in { let PPC970_Unit = 2, mayStore = 1 in {
let Interpretation64Bit = 1 in { let Interpretation64Bit = 1 in {
def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
"stbu $rS, $dst", LdStStoreUpd, []>, "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
"sthu $rS, $dst", LdStStoreUpd, []>, "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
"stwu $rS, $dst", LdStStoreUpd, []>, "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst), def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst),
"stdu $rS, $dst", LdStSTDU, []>, "stdu $rS, $dst", IIC_LdStSTDU, []>,
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
isPPC64; isPPC64;
def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
"stbux $rS, $dst", LdStStoreUpd, []>, "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
"sthux $rS, $dst", LdStStoreUpd, []>, "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
"stwux $rS, $dst", LdStStoreUpd, []>, "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
PPC970_DGroup_Cracked; PPC970_DGroup_Cracked;
} // Interpretation64Bit } // Interpretation64Bit
def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
"stdux $rS, $dst", LdStSTDU, []>, "stdux $rS, $dst", IIC_LdStSTDU, []>,
RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
PPC970_DGroup_Cracked, isPPC64; PPC970_DGroup_Cracked, isPPC64;
} }
@@ -966,29 +971,29 @@ def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
let PPC970_Unit = 3, neverHasSideEffects = 1, let PPC970_Unit = 3, neverHasSideEffects = 1,
Uses = [RM] in { // FPU Operations. Uses = [RM] in { // FPU Operations.
defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),
"fcfid", "$frD, $frB", FPGeneral, "fcfid", "$frD, $frB", IIC_FPGeneral,
[(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64; [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB), defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB),
"fctid", "$frD, $frB", FPGeneral, "fctid", "$frD, $frB", IIC_FPGeneral,
[]>, isPPC64; []>, isPPC64;
defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
"fctidz", "$frD, $frB", FPGeneral, "fctidz", "$frD, $frB", IIC_FPGeneral,
[(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64; [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB),
"fcfidu", "$frD, $frB", FPGeneral, "fcfidu", "$frD, $frB", IIC_FPGeneral,
[(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64; [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64;
defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB),
"fcfids", "$frD, $frB", FPGeneral, "fcfids", "$frD, $frB", IIC_FPGeneral,
[(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64; [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64;
defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB),
"fcfidus", "$frD, $frB", FPGeneral, "fcfidus", "$frD, $frB", IIC_FPGeneral,
[(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64; [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64;
defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB),
"fctiduz", "$frD, $frB", FPGeneral, "fctiduz", "$frD, $frB", IIC_FPGeneral,
[(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64; [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64;
defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB),
"fctiwuz", "$frD, $frB", FPGeneral, "fctiwuz", "$frD, $frB", IIC_FPGeneral,
[(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64; [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64;
} }

158
lib/Target/PowerPC/PPCInstrAltivec.td
View File

@@ -164,7 +164,7 @@ def vecspltisw : PatLeaf<(build_vector), [{
// VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type. // VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type.
class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty> class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty>
: VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
!strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP, !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
[(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>; [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>;
// VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the // VA1a_Int_Ty2 - A VAForm_1a intrinsic definition where the type of the
@@ -172,7 +172,7 @@ class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty>
class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
ValueType InTy> ValueType InTy>
: VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
!strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP, !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
[(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>; [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>;
// VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two // VA1a_Int_Ty3 - A VAForm_1a intrinsic definition where there are two
@@ -180,14 +180,14 @@ class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy, class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
ValueType In1Ty, ValueType In2Ty> ValueType In1Ty, ValueType In2Ty>
: VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC), : VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
!strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP, !strconcat(opc, " $vD, $vA, $vB, $vC"), IIC_VecFP,
[(set OutTy:$vD, [(set OutTy:$vD,
(IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>; (IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>;
// VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type. // VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type.
class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty> class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
: VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
!strconcat(opc, " $vD, $vA, $vB"), VecFP, !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
[(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>; [(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>;
// VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the // VX1_Int_Ty2 - A VXForm_1 intrinsic definition where the type of the
@@ -195,7 +195,7 @@ class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
ValueType InTy> ValueType InTy>
: VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
!strconcat(opc, " $vD, $vA, $vB"), VecFP, !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
[(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>; [(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>;
// VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two // VX1_Int_Ty3 - A VXForm_1 intrinsic definition where there are two
@@ -203,13 +203,13 @@ class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
ValueType In1Ty, ValueType In2Ty> ValueType In1Ty, ValueType In2Ty>
: VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), : VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
!strconcat(opc, " $vD, $vA, $vB"), VecFP, !strconcat(opc, " $vD, $vA, $vB"), IIC_VecFP,
[(set OutTy:$vD, (IntID In1Ty:$vA, In2Ty:$vB))]>; [(set OutTy:$vD, (IntID In1Ty:$vA, In2Ty:$vB))]>;
// VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type. // VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type.
class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID> class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID>
: VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB), : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB),
!strconcat(opc, " $vD, $vB"), VecFP, !strconcat(opc, " $vD, $vB"), IIC_VecFP,
[(set v4f32:$vD, (IntID v4f32:$vB))]>; [(set v4f32:$vD, (IntID v4f32:$vB))]>;
// VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the // VX2_Int_Ty2 - A VXForm_2 intrinsic definition where the type of the
@@ -217,7 +217,7 @@ class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID>
class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy, class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
ValueType InTy> ValueType InTy>
: VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB), : VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB),
!strconcat(opc, " $vD, $vB"), VecFP, !strconcat(opc, " $vD, $vB"), IIC_VecFP,
[(set OutTy:$vD, (IntID InTy:$vB))]>; [(set OutTy:$vD, (IntID InTy:$vB))]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@@ -229,109 +229,109 @@ let Predicates = [HasAltivec] in {
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
def DSS : DSS_Form<822, (outs), def DSS : DSS_Form<822, (outs),
(ins u5imm:$ZERO0, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2), (ins u5imm:$ZERO0, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2),
"dss $STRM", LdStLoad /*FIXME*/, []>, "dss $STRM", IIC_LdStLoad /*FIXME*/, []>,
Deprecated<DeprecatedDST>; Deprecated<DeprecatedDST>;
def DSSALL : DSS_Form<822, (outs), def DSSALL : DSS_Form<822, (outs),
(ins u5imm:$ONE, u5imm:$ZERO0,u5imm:$ZERO1,u5imm:$ZERO2), (ins u5imm:$ONE, u5imm:$ZERO0,u5imm:$ZERO1,u5imm:$ZERO2),
"dssall", LdStLoad /*FIXME*/, []>, "dssall", IIC_LdStLoad /*FIXME*/, []>,
Deprecated<DeprecatedDST>; Deprecated<DeprecatedDST>;
def DST : DSS_Form<342, (outs), def DST : DSS_Form<342, (outs),
(ins u5imm:$ZERO, u5imm:$STRM, gprc:$rA, gprc:$rB), (ins u5imm:$ZERO, u5imm:$STRM, gprc:$rA, gprc:$rB),
"dst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>, "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>,
Deprecated<DeprecatedDST>; Deprecated<DeprecatedDST>;
def DSTT : DSS_Form<342, (outs), def DSTT : DSS_Form<342, (outs),
(ins u5imm:$ONE, u5imm:$STRM, gprc:$rA, gprc:$rB), (ins u5imm:$ONE, u5imm:$STRM, gprc:$rA, gprc:$rB),
"dstt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>, "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>,
Deprecated<DeprecatedDST>; Deprecated<DeprecatedDST>;
def DSTST : DSS_Form<374, (outs), def DSTST : DSS_Form<374, (outs),
(ins u5imm:$ZERO, u5imm:$STRM, gprc:$rA, gprc:$rB), (ins u5imm:$ZERO, u5imm:$STRM, gprc:$rA, gprc:$rB),
"dstst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>, "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>,
Deprecated<DeprecatedDST>; Deprecated<DeprecatedDST>;
def DSTSTT : DSS_Form<374, (outs), def DSTSTT : DSS_Form<374, (outs),
(ins u5imm:$ONE, u5imm:$STRM, gprc:$rA, gprc:$rB), (ins u5imm:$ONE, u5imm:$STRM, gprc:$rA, gprc:$rB),
"dststt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>, "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>,
Deprecated<DeprecatedDST>; Deprecated<DeprecatedDST>;
def DST64 : DSS_Form<342, (outs), def DST64 : DSS_Form<342, (outs),
(ins u5imm:$ZERO, u5imm:$STRM, g8rc:$rA, gprc:$rB), (ins u5imm:$ZERO, u5imm:$STRM, g8rc:$rA, gprc:$rB),
"dst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>, "dst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>,
Deprecated<DeprecatedDST>; Deprecated<DeprecatedDST>;
def DSTT64 : DSS_Form<342, (outs), def DSTT64 : DSS_Form<342, (outs),
(ins u5imm:$ONE, u5imm:$STRM, g8rc:$rA, gprc:$rB), (ins u5imm:$ONE, u5imm:$STRM, g8rc:$rA, gprc:$rB),
"dstt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>, "dstt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>,
Deprecated<DeprecatedDST>; Deprecated<DeprecatedDST>;
def DSTST64 : DSS_Form<374, (outs), def DSTST64 : DSS_Form<374, (outs),
(ins u5imm:$ZERO, u5imm:$STRM, g8rc:$rA, gprc:$rB), (ins u5imm:$ZERO, u5imm:$STRM, g8rc:$rA, gprc:$rB),
"dstst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>, "dstst $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>,
Deprecated<DeprecatedDST>; Deprecated<DeprecatedDST>;
def DSTSTT64 : DSS_Form<374, (outs), def DSTSTT64 : DSS_Form<374, (outs),
(ins u5imm:$ONE, u5imm:$STRM, g8rc:$rA, gprc:$rB), (ins u5imm:$ONE, u5imm:$STRM, g8rc:$rA, gprc:$rB),
"dststt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>, "dststt $rA, $rB, $STRM", IIC_LdStLoad /*FIXME*/, []>,
Deprecated<DeprecatedDST>; Deprecated<DeprecatedDST>;
} }
def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins), def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins),
"mfvscr $vD", LdStStore, "mfvscr $vD", IIC_LdStStore,
[(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>; [(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>;
def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$vB), def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$vB),
"mtvscr $vB", LdStLoad, "mtvscr $vB", IIC_LdStLoad,
[(int_ppc_altivec_mtvscr v4i32:$vB)]>; [(int_ppc_altivec_mtvscr v4i32:$vB)]>;
let canFoldAsLoad = 1, PPC970_Unit = 2 in { // Loads. let canFoldAsLoad = 1, PPC970_Unit = 2 in { // Loads.
def LVEBX: XForm_1<31, 7, (outs vrrc:$vD), (ins memrr:$src), def LVEBX: XForm_1<31, 7, (outs vrrc:$vD), (ins memrr:$src),
"lvebx $vD, $src", LdStLoad, "lvebx $vD, $src", IIC_LdStLoad,
[(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>; [(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
def LVEHX: XForm_1<31, 39, (outs vrrc:$vD), (ins memrr:$src), def LVEHX: XForm_1<31, 39, (outs vrrc:$vD), (ins memrr:$src),
"lvehx $vD, $src", LdStLoad, "lvehx $vD, $src", IIC_LdStLoad,
[(set v8i16:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>; [(set v8i16:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
def LVEWX: XForm_1<31, 71, (outs vrrc:$vD), (ins memrr:$src), def LVEWX: XForm_1<31, 71, (outs vrrc:$vD), (ins memrr:$src),
"lvewx $vD, $src", LdStLoad, "lvewx $vD, $src", IIC_LdStLoad,
[(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>; [(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
def LVX : XForm_1<31, 103, (outs vrrc:$vD), (ins memrr:$src), def LVX : XForm_1<31, 103, (outs vrrc:$vD), (ins memrr:$src),
"lvx $vD, $src", LdStLoad, "lvx $vD, $src", IIC_LdStLoad,
[(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>; [(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
def LVXL : XForm_1<31, 359, (outs vrrc:$vD), (ins memrr:$src), def LVXL : XForm_1<31, 359, (outs vrrc:$vD), (ins memrr:$src),
"lvxl $vD, $src", LdStLoad, "lvxl $vD, $src", IIC_LdStLoad,
[(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>; [(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
} }
def LVSL : XForm_1<31, 6, (outs vrrc:$vD), (ins memrr:$src), def LVSL : XForm_1<31, 6, (outs vrrc:$vD), (ins memrr:$src),
"lvsl $vD, $src", LdStLoad, "lvsl $vD, $src", IIC_LdStLoad,
[(set v16i8:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>, [(set v16i8:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>,
PPC970_Unit_LSU; PPC970_Unit_LSU;
def LVSR : XForm_1<31, 38, (outs vrrc:$vD), (ins memrr:$src), def LVSR : XForm_1<31, 38, (outs vrrc:$vD), (ins memrr:$src),
"lvsr $vD, $src", LdStLoad, "lvsr $vD, $src", IIC_LdStLoad,
[(set v16i8:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>, [(set v16i8:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
PPC970_Unit_LSU; PPC970_Unit_LSU;
let PPC970_Unit = 2 in { // Stores. let PPC970_Unit = 2 in { // Stores.
def STVEBX: XForm_8<31, 135, (outs), (ins vrrc:$rS, memrr:$dst), def STVEBX: XForm_8<31, 135, (outs), (ins vrrc:$rS, memrr:$dst),
"stvebx $rS, $dst", LdStStore, "stvebx $rS, $dst", IIC_LdStStore,
[(int_ppc_altivec_stvebx v16i8:$rS, xoaddr:$dst)]>; [(int_ppc_altivec_stvebx v16i8:$rS, xoaddr:$dst)]>;
def STVEHX: XForm_8<31, 167, (outs), (ins vrrc:$rS, memrr:$dst), def STVEHX: XForm_8<31, 167, (outs), (ins vrrc:$rS, memrr:$dst),
"stvehx $rS, $dst", LdStStore, "stvehx $rS, $dst", IIC_LdStStore,
[(int_ppc_altivec_stvehx v8i16:$rS, xoaddr:$dst)]>; [(int_ppc_altivec_stvehx v8i16:$rS, xoaddr:$dst)]>;
def STVEWX: XForm_8<31, 199, (outs), (ins vrrc:$rS, memrr:$dst), def STVEWX: XForm_8<31, 199, (outs), (ins vrrc:$rS, memrr:$dst),
"stvewx $rS, $dst", LdStStore, "stvewx $rS, $dst", IIC_LdStStore,
[(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>; [(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>;
def STVX : XForm_8<31, 231, (outs), (ins vrrc:$rS, memrr:$dst), def STVX : XForm_8<31, 231, (outs), (ins vrrc:$rS, memrr:$dst),
"stvx $rS, $dst", LdStStore, "stvx $rS, $dst", IIC_LdStStore,
[(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>; [(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>;
def STVXL : XForm_8<31, 487, (outs), (ins vrrc:$rS, memrr:$dst), def STVXL : XForm_8<31, 487, (outs), (ins vrrc:$rS, memrr:$dst),
"stvxl $rS, $dst", LdStStore, "stvxl $rS, $dst", IIC_LdStStore,
[(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>; [(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>;
} }
let PPC970_Unit = 5 in { // VALU Operations. let PPC970_Unit = 5 in { // VALU Operations.
// VA-Form instructions. 3-input AltiVec ops. // VA-Form instructions. 3-input AltiVec ops.
def VMADDFP : VAForm_1<46, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), def VMADDFP : VAForm_1<46, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB),
"vmaddfp $vD, $vA, $vC, $vB", VecFP, "vmaddfp $vD, $vA, $vC, $vB", IIC_VecFP,
[(set v4f32:$vD, [(set v4f32:$vD,
(fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>; (fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>;
// FIXME: The fma+fneg pattern won't match because fneg is not legal. // FIXME: The fma+fneg pattern won't match because fneg is not legal.
def VNMSUBFP: VAForm_1<47, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB), def VNMSUBFP: VAForm_1<47, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB),
"vnmsubfp $vD, $vA, $vC, $vB", VecFP, "vnmsubfp $vD, $vA, $vC, $vB", IIC_VecFP,
[(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC, [(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC,
(fneg v4f32:$vB))))]>; (fneg v4f32:$vB))))]>;
@@ -346,23 +346,23 @@ def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>;
// Shuffles. // Shuffles.
def VSLDOI : VAForm_2<44, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u5imm:$SH), def VSLDOI : VAForm_2<44, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u5imm:$SH),
"vsldoi $vD, $vA, $vB, $SH", VecFP, "vsldoi $vD, $vA, $vB, $SH", IIC_VecFP,
[(set v16i8:$vD, [(set v16i8:$vD,
(vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB))]>; (vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB))]>;
// VX-Form instructions. AltiVec arithmetic ops. // VX-Form instructions. AltiVec arithmetic ops.
def VADDFP : VXForm_1<10, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VADDFP : VXForm_1<10, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vaddfp $vD, $vA, $vB", VecFP, "vaddfp $vD, $vA, $vB", IIC_VecFP,
[(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>; [(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>;
def VADDUBM : VXForm_1<0, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VADDUBM : VXForm_1<0, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vaddubm $vD, $vA, $vB", VecGeneral, "vaddubm $vD, $vA, $vB", IIC_VecGeneral,
[(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>; [(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>;
def VADDUHM : VXForm_1<64, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VADDUHM : VXForm_1<64, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vadduhm $vD, $vA, $vB", VecGeneral, "vadduhm $vD, $vA, $vB", IIC_VecGeneral,
[(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>; [(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>;
def VADDUWM : VXForm_1<128, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VADDUWM : VXForm_1<128, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vadduwm $vD, $vA, $vB", VecGeneral, "vadduwm $vD, $vA, $vB", IIC_VecGeneral,
[(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>; [(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>;
def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>; def VADDCUW : VX1_Int_Ty<384, "vaddcuw", int_ppc_altivec_vaddcuw, v4i32>;
@@ -375,27 +375,27 @@ def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>;
def VAND : VXForm_1<1028, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VAND : VXForm_1<1028, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vand $vD, $vA, $vB", VecFP, "vand $vD, $vA, $vB", IIC_VecFP,
[(set v4i32:$vD, (and v4i32:$vA, v4i32:$vB))]>; [(set v4i32:$vD, (and v4i32:$vA, v4i32:$vB))]>;
def VANDC : VXForm_1<1092, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VANDC : VXForm_1<1092, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vandc $vD, $vA, $vB", VecFP, "vandc $vD, $vA, $vB", IIC_VecFP,
[(set v4i32:$vD, (and v4i32:$vA, [(set v4i32:$vD, (and v4i32:$vA,
(vnot_ppc v4i32:$vB)))]>; (vnot_ppc v4i32:$vB)))]>;
def VCFSX : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), def VCFSX : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
"vcfsx $vD, $vB, $UIMM", VecFP, "vcfsx $vD, $vB, $UIMM", IIC_VecFP,
[(set v4f32:$vD, [(set v4f32:$vD,
(int_ppc_altivec_vcfsx v4i32:$vB, imm:$UIMM))]>; (int_ppc_altivec_vcfsx v4i32:$vB, imm:$UIMM))]>;
def VCFUX : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), def VCFUX : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
"vcfux $vD, $vB, $UIMM", VecFP, "vcfux $vD, $vB, $UIMM", IIC_VecFP,
[(set v4f32:$vD, [(set v4f32:$vD,
(int_ppc_altivec_vcfux v4i32:$vB, imm:$UIMM))]>; (int_ppc_altivec_vcfux v4i32:$vB, imm:$UIMM))]>;
def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
"vctsxs $vD, $vB, $UIMM", VecFP, "vctsxs $vD, $vB, $UIMM", IIC_VecFP,
[(set v4i32:$vD, [(set v4i32:$vD,
(int_ppc_altivec_vctsxs v4f32:$vB, imm:$UIMM))]>; (int_ppc_altivec_vctsxs v4f32:$vB, imm:$UIMM))]>;
def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
"vctuxs $vD, $vB, $UIMM", VecFP, "vctuxs $vD, $vB, $UIMM", IIC_VecFP,
[(set v4i32:$vD, [(set v4i32:$vD,
(int_ppc_altivec_vctuxs v4f32:$vB, imm:$UIMM))]>; (int_ppc_altivec_vctuxs v4f32:$vB, imm:$UIMM))]>;
@@ -404,19 +404,19 @@ def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
// to floating-point (sint_to_fp/uint_to_fp) conversions. // to floating-point (sint_to_fp/uint_to_fp) conversions.
let isCodeGenOnly = 1, VA = 0 in { let isCodeGenOnly = 1, VA = 0 in {
def VCFSX_0 : VXForm_1<842, (outs vrrc:$vD), (ins vrrc:$vB), def VCFSX_0 : VXForm_1<842, (outs vrrc:$vD), (ins vrrc:$vB),
"vcfsx $vD, $vB, 0", VecFP, "vcfsx $vD, $vB, 0", IIC_VecFP,
[(set v4f32:$vD, [(set v4f32:$vD,
(int_ppc_altivec_vcfsx v4i32:$vB, 0))]>; (int_ppc_altivec_vcfsx v4i32:$vB, 0))]>;
def VCTUXS_0 : VXForm_1<906, (outs vrrc:$vD), (ins vrrc:$vB), def VCTUXS_0 : VXForm_1<906, (outs vrrc:$vD), (ins vrrc:$vB),
"vctuxs $vD, $vB, 0", VecFP, "vctuxs $vD, $vB, 0", IIC_VecFP,
[(set v4i32:$vD, [(set v4i32:$vD,
(int_ppc_altivec_vctuxs v4f32:$vB, 0))]>; (int_ppc_altivec_vctuxs v4f32:$vB, 0))]>;
def VCFUX_0 : VXForm_1<778, (outs vrrc:$vD), (ins vrrc:$vB), def VCFUX_0 : VXForm_1<778, (outs vrrc:$vD), (ins vrrc:$vB),
"vcfux $vD, $vB, 0", VecFP, "vcfux $vD, $vB, 0", IIC_VecFP,
[(set v4f32:$vD, [(set v4f32:$vD,
(int_ppc_altivec_vcfux v4i32:$vB, 0))]>; (int_ppc_altivec_vcfux v4i32:$vB, 0))]>;
def VCTSXS_0 : VXForm_1<970, (outs vrrc:$vD), (ins vrrc:$vB), def VCTSXS_0 : VXForm_1<970, (outs vrrc:$vD), (ins vrrc:$vB),
"vctsxs $vD, $vB, 0", VecFP, "vctsxs $vD, $vB, 0", IIC_VecFP,
[(set v4i32:$vD, [(set v4i32:$vD,
(int_ppc_altivec_vctsxs v4f32:$vB, 0))]>; (int_ppc_altivec_vctsxs v4f32:$vB, 0))]>;
} }
@@ -446,22 +446,22 @@ def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>;
def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>; def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>;
def VMRGHB : VXForm_1< 12, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMRGHB : VXForm_1< 12, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vmrghb $vD, $vA, $vB", VecFP, "vmrghb $vD, $vA, $vB", IIC_VecFP,
[(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>; [(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>;
def VMRGHH : VXForm_1< 76, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMRGHH : VXForm_1< 76, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vmrghh $vD, $vA, $vB", VecFP, "vmrghh $vD, $vA, $vB", IIC_VecFP,
[(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>; [(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>;
def VMRGHW : VXForm_1<140, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMRGHW : VXForm_1<140, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vmrghw $vD, $vA, $vB", VecFP, "vmrghw $vD, $vA, $vB", IIC_VecFP,
[(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>; [(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>;
def VMRGLB : VXForm_1<268, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMRGLB : VXForm_1<268, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vmrglb $vD, $vA, $vB", VecFP, "vmrglb $vD, $vA, $vB", IIC_VecFP,
[(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>; [(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>;
def VMRGLH : VXForm_1<332, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMRGLH : VXForm_1<332, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vmrglh $vD, $vA, $vB", VecFP, "vmrglh $vD, $vA, $vB", IIC_VecFP,
[(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>; [(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>;
def VMRGLW : VXForm_1<396, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VMRGLW : VXForm_1<396, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vmrglw $vD, $vA, $vB", VecFP, "vmrglw $vD, $vA, $vB", IIC_VecFP,
[(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>; [(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>;
def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm, def VMSUMMBM : VA1a_Int_Ty3<37, "vmsummbm", int_ppc_altivec_vmsummbm,
@@ -504,16 +504,16 @@ def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>;
def VSUBCUW : VX1_Int_Ty<1408, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>; def VSUBCUW : VX1_Int_Ty<1408, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>;
def VSUBFP : VXForm_1<74, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VSUBFP : VXForm_1<74, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vsubfp $vD, $vA, $vB", VecGeneral, "vsubfp $vD, $vA, $vB", IIC_VecGeneral,
[(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>; [(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>;
def VSUBUBM : VXForm_1<1024, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VSUBUBM : VXForm_1<1024, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vsububm $vD, $vA, $vB", VecGeneral, "vsububm $vD, $vA, $vB", IIC_VecGeneral,
[(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>; [(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>;
def VSUBUHM : VXForm_1<1088, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VSUBUHM : VXForm_1<1088, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vsubuhm $vD, $vA, $vB", VecGeneral, "vsubuhm $vD, $vA, $vB", IIC_VecGeneral,
[(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>; [(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>;
def VSUBUWM : VXForm_1<1152, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VSUBUWM : VXForm_1<1152, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vsubuwm $vD, $vA, $vB", VecGeneral, "vsubuwm $vD, $vA, $vB", IIC_VecGeneral,
[(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>; [(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>;
def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>; def VSUBSBS : VX1_Int_Ty<1792, "vsubsbs" , int_ppc_altivec_vsubsbs, v16i8>;
@@ -534,14 +534,14 @@ def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs,
v4i32, v16i8, v4i32>; v4i32, v16i8, v4i32>;
def VNOR : VXForm_1<1284, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VNOR : VXForm_1<1284, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vnor $vD, $vA, $vB", VecFP, "vnor $vD, $vA, $vB", IIC_VecFP,
[(set v4i32:$vD, (vnot_ppc (or v4i32:$vA, [(set v4i32:$vD, (vnot_ppc (or v4i32:$vA,
v4i32:$vB)))]>; v4i32:$vB)))]>;
def VOR : VXForm_1<1156, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VOR : VXForm_1<1156, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vor $vD, $vA, $vB", VecFP, "vor $vD, $vA, $vB", IIC_VecFP,
[(set v4i32:$vD, (or v4i32:$vA, v4i32:$vB))]>; [(set v4i32:$vD, (or v4i32:$vA, v4i32:$vB))]>;
def VXOR : VXForm_1<1220, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VXOR : VXForm_1<1220, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vxor $vD, $vA, $vB", VecFP, "vxor $vD, $vA, $vB", IIC_VecFP,
[(set v4i32:$vD, (xor v4i32:$vA, v4i32:$vB))]>; [(set v4i32:$vD, (xor v4i32:$vA, v4i32:$vB))]>;
def VRLB : VX1_Int_Ty< 4, "vrlb", int_ppc_altivec_vrlb, v16i8>; def VRLB : VX1_Int_Ty< 4, "vrlb", int_ppc_altivec_vrlb, v16i8>;
@@ -556,15 +556,15 @@ def VSLH : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>;
def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>; def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>;
def VSPLTB : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), def VSPLTB : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
"vspltb $vD, $vB, $UIMM", VecPerm, "vspltb $vD, $vB, $UIMM", IIC_VecPerm,
[(set v16i8:$vD, [(set v16i8:$vD,
(vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>; (vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>;
def VSPLTH : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), def VSPLTH : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
"vsplth $vD, $vB, $UIMM", VecPerm, "vsplth $vD, $vB, $UIMM", IIC_VecPerm,
[(set v16i8:$vD, [(set v16i8:$vD,
(vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>; (vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>;
def VSPLTW : VXForm_1<652, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB), def VSPLTW : VXForm_1<652, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
"vspltw $vD, $vB, $UIMM", VecPerm, "vspltw $vD, $vB, $UIMM", IIC_VecPerm,
[(set v16i8:$vD, [(set v16i8:$vD,
(vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>; (vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>;
@@ -580,13 +580,13 @@ def VSRW : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>;
def VSPLTISB : VXForm_3<780, (outs vrrc:$vD), (ins s5imm:$SIMM), def VSPLTISB : VXForm_3<780, (outs vrrc:$vD), (ins s5imm:$SIMM),
"vspltisb $vD, $SIMM", VecPerm, "vspltisb $vD, $SIMM", IIC_VecPerm,
[(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>; [(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>;
def VSPLTISH : VXForm_3<844, (outs vrrc:$vD), (ins s5imm:$SIMM), def VSPLTISH : VXForm_3<844, (outs vrrc:$vD), (ins s5imm:$SIMM),
"vspltish $vD, $SIMM", VecPerm, "vspltish $vD, $SIMM", IIC_VecPerm,
[(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>; [(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>;
def VSPLTISW : VXForm_3<908, (outs vrrc:$vD), (ins s5imm:$SIMM), def VSPLTISW : VXForm_3<908, (outs vrrc:$vD), (ins s5imm:$SIMM),
"vspltisw $vD, $SIMM", VecPerm, "vspltisw $vD, $SIMM", IIC_VecPerm,
[(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>; [(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>;
// Vector Pack. // Vector Pack.
@@ -601,13 +601,13 @@ def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss,
def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus, def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus,
v8i16, v4i32>; v8i16, v4i32>;
def VPKUHUM : VXForm_1<14, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VPKUHUM : VXForm_1<14, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vpkuhum $vD, $vA, $vB", VecFP, "vpkuhum $vD, $vA, $vB", IIC_VecFP,
[(set v16i8:$vD, [(set v16i8:$vD,
(vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>; (vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>;
def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus, def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus,
v16i8, v8i16>; v16i8, v8i16>;
def VPKUWUM : VXForm_1<78, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), def VPKUWUM : VXForm_1<78, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
"vpkuwum $vD, $vA, $vB", VecFP, "vpkuwum $vD, $vA, $vB", IIC_VecFP,
[(set v16i8:$vD, [(set v16i8:$vD,
(vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>; (vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>;
def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus, def VPKUWUS : VX1_Int_Ty2<206, "vpkuwus", int_ppc_altivec_vpkuwus,
@@ -631,10 +631,12 @@ def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh,
// Altivec Comparisons. // Altivec Comparisons.
class VCMP<bits<10> xo, string asmstr, ValueType Ty> class VCMP<bits<10> xo, string asmstr, ValueType Ty>
: VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),asmstr,VecFPCompare, : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
IIC_VecFPCompare,
[(set Ty:$vD, (Ty (PPCvcmp Ty:$vA, Ty:$vB, xo)))]>; [(set Ty:$vD, (Ty (PPCvcmp Ty:$vA, Ty:$vB, xo)))]>;
class VCMPo<bits<10> xo, string asmstr, ValueType Ty> class VCMPo<bits<10> xo, string asmstr, ValueType Ty>
: VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),asmstr,VecFPCompare, : VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB), asmstr,
IIC_VecFPCompare,
[(set Ty:$vD, (Ty (PPCvcmp_o Ty:$vA, Ty:$vB, xo)))]> { [(set Ty:$vD, (Ty (PPCvcmp_o Ty:$vA, Ty:$vB, xo)))]> {
let Defs = [CR6]; let Defs = [CR6];
let RC = 1; let RC = 1;
@@ -676,24 +678,24 @@ def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins), def V_SET0B : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
"vxor $vD, $vD, $vD", VecFP, "vxor $vD, $vD, $vD", IIC_VecFP,
[(set v16i8:$vD, (v16i8 immAllZerosV))]>; [(set v16i8:$vD, (v16i8 immAllZerosV))]>;
def V_SET0H : VXForm_setzero<1220, (outs vrrc:$vD), (ins), def V_SET0H : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
"vxor $vD, $vD, $vD", VecFP, "vxor $vD, $vD, $vD", IIC_VecFP,
[(set v8i16:$vD, (v8i16 immAllZerosV))]>; [(set v8i16:$vD, (v8i16 immAllZerosV))]>;
def V_SET0 : VXForm_setzero<1220, (outs vrrc:$vD), (ins), def V_SET0 : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
"vxor $vD, $vD, $vD", VecFP, "vxor $vD, $vD, $vD", IIC_VecFP,
[(set v4i32:$vD, (v4i32 immAllZerosV))]>; [(set v4i32:$vD, (v4i32 immAllZerosV))]>;
let IMM=-1 in { let IMM=-1 in {
def V_SETALLONESB : VXForm_3<908, (outs vrrc:$vD), (ins), def V_SETALLONESB : VXForm_3<908, (outs vrrc:$vD), (ins),
"vspltisw $vD, -1", VecFP, "vspltisw $vD, -1", IIC_VecFP,
[(set v16i8:$vD, (v16i8 immAllOnesV))]>; [(set v16i8:$vD, (v16i8 immAllOnesV))]>;
def V_SETALLONESH : VXForm_3<908, (outs vrrc:$vD), (ins), def V_SETALLONESH : VXForm_3<908, (outs vrrc:$vD), (ins),
"vspltisw $vD, -1", VecFP, "vspltisw $vD, -1", IIC_VecFP,
[(set v8i16:$vD, (v8i16 immAllOnesV))]>; [(set v8i16:$vD, (v8i16 immAllOnesV))]>;
def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins), def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins),
"vspltisw $vD, -1", VecFP, "vspltisw $vD, -1", IIC_VecFP,
[(set v4i32:$vD, (v4i32 immAllOnesV))]>; [(set v4i32:$vD, (v4i32 immAllOnesV))]>;
} }
} }

6
lib/Target/PowerPC/PPCInstrFormats.td
View File

@@ -109,7 +109,7 @@ class IForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr,
// 1.7.2 B-Form // 1.7.2 B-Form
class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr> class BForm<bits<6> opcode, bit aa, bit lk, dag OOL, dag IOL, string asmstr>
: I<opcode, OOL, IOL, asmstr, BrB> { : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
bits<7> BIBO; // 2 bits of BI and 5 bits of BO. bits<7> BIBO; // 2 bits of BI and 5 bits of BO.
bits<3> CR; bits<3> CR;
bits<14> BD; bits<14> BD;
@@ -135,7 +135,7 @@ class BForm_1<bits<6> opcode, bits<5> bo, bit aa, bit lk, dag OOL, dag IOL,
class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk, class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
dag OOL, dag IOL, string asmstr> dag OOL, dag IOL, string asmstr>
: I<opcode, OOL, IOL, asmstr, BrB> { : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
bits<14> BD; bits<14> BD;
let Inst{6-10} = bo; let Inst{6-10} = bo;
@@ -147,7 +147,7 @@ class BForm_2<bits<6> opcode, bits<5> bo, bits<5> bi, bit aa, bit lk,
class BForm_3<bits<6> opcode, bit aa, bit lk, class BForm_3<bits<6> opcode, bit aa, bit lk,
dag OOL, dag IOL, string asmstr> dag OOL, dag IOL, string asmstr>
: I<opcode, OOL, IOL, asmstr, BrB> { : I<opcode, OOL, IOL, asmstr, IIC_BrB> {
bits<5> BO; bits<5> BO;
bits<5> BI; bits<5> BI;
bits<14> BD; bits<14> BD;

528
lib/Target/PowerPC/PPCInstrInfo.td
View File

File diff suppressed because it is too large Load Diff

958
lib/Target/PowerPC/PPCSchedule.td
View File

@@ -25,97 +25,97 @@ def VFPU : FuncUnit; // vector floating point unit
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Instruction Itinerary classes used for PowerPC // Instruction Itinerary classes used for PowerPC
// //
def IntSimple : InstrItinClass; def IIC_IntSimple : InstrItinClass;
def IntGeneral : InstrItinClass; def IIC_IntGeneral : InstrItinClass;
def IntCompare : InstrItinClass; def IIC_IntCompare : InstrItinClass;
def IntDivD : InstrItinClass; def IIC_IntDivD : InstrItinClass;
def IntDivW : InstrItinClass; def IIC_IntDivW : InstrItinClass;
def IntMFFS : InstrItinClass; def IIC_IntMFFS : InstrItinClass;
def IntMFVSCR : InstrItinClass; def IIC_IntMFVSCR : InstrItinClass;
def IntMTFSB0 : InstrItinClass; def IIC_IntMTFSB0 : InstrItinClass;
def IntMTSRD : InstrItinClass; def IIC_IntMTSRD : InstrItinClass;
def IntMulHD : InstrItinClass; def IIC_IntMulHD : InstrItinClass;
def IntMulHW : InstrItinClass; def IIC_IntMulHW : InstrItinClass;
def IntMulHWU : InstrItinClass; def IIC_IntMulHWU : InstrItinClass;
def IntMulLI : InstrItinClass; def IIC_IntMulLI : InstrItinClass;
def IntRFID : InstrItinClass; def IIC_IntRFID : InstrItinClass;
def IntRotateD : InstrItinClass; def IIC_IntRotateD : InstrItinClass;
def IntRotateDI : InstrItinClass; def IIC_IntRotateDI : InstrItinClass;
def IntRotate : InstrItinClass; def IIC_IntRotate : InstrItinClass;
def IntShift : InstrItinClass; def IIC_IntShift : InstrItinClass;
def IntTrapD : InstrItinClass; def IIC_IntTrapD : InstrItinClass;
def IntTrapW : InstrItinClass; def IIC_IntTrapW : InstrItinClass;
def BrB : InstrItinClass; def IIC_BrB : InstrItinClass;
def BrCR : InstrItinClass; def IIC_BrCR : InstrItinClass;
def BrMCR : InstrItinClass; def IIC_BrMCR : InstrItinClass;
def BrMCRX : InstrItinClass; def IIC_BrMCRX : InstrItinClass;
def LdStDCBA : InstrItinClass; def IIC_LdStDCBA : InstrItinClass;
def LdStDCBF : InstrItinClass; def IIC_LdStDCBF : InstrItinClass;
def LdStDCBI : InstrItinClass; def IIC_LdStDCBI : InstrItinClass;
def LdStLoad : InstrItinClass; def IIC_LdStLoad : InstrItinClass;
def LdStLoadUpd : InstrItinClass; def IIC_LdStLoadUpd : InstrItinClass;
def LdStStore : InstrItinClass; def IIC_LdStStore : InstrItinClass;
def LdStStoreUpd : InstrItinClass; def IIC_LdStStoreUpd : InstrItinClass;
def LdStDSS : InstrItinClass; def IIC_LdStDSS : InstrItinClass;
def LdStICBI : InstrItinClass; def IIC_LdStICBI : InstrItinClass;
def LdStLD : InstrItinClass; def IIC_LdStLD : InstrItinClass;
def LdStLDU : InstrItinClass; def IIC_LdStLDU : InstrItinClass;
def LdStLDARX : InstrItinClass; def IIC_LdStLDARX : InstrItinClass;
def LdStLFD : InstrItinClass; def IIC_LdStLFD : InstrItinClass;
def LdStLFDU : InstrItinClass; def IIC_LdStLFDU : InstrItinClass;
def LdStLHA : InstrItinClass; def IIC_LdStLHA : InstrItinClass;
def LdStLHAU : InstrItinClass; def IIC_LdStLHAU : InstrItinClass;
def LdStLMW : InstrItinClass; def IIC_LdStLMW : InstrItinClass;
def LdStLVecX : InstrItinClass; def IIC_LdStLVecX : InstrItinClass;
def LdStLWA : InstrItinClass; def IIC_LdStLWA : InstrItinClass;
def LdStLWARX : InstrItinClass; def IIC_LdStLWARX : InstrItinClass;
def LdStSLBIA : InstrItinClass; def IIC_LdStSLBIA : InstrItinClass;
def LdStSLBIE : InstrItinClass; def IIC_LdStSLBIE : InstrItinClass;
def LdStSTD : InstrItinClass; def IIC_LdStSTD : InstrItinClass;
def LdStSTDCX : InstrItinClass; def IIC_LdStSTDCX : InstrItinClass;
def LdStSTDU : InstrItinClass; def IIC_LdStSTDU : InstrItinClass;
def LdStSTFD : InstrItinClass; def IIC_LdStSTFD : InstrItinClass;
def LdStSTFDU : InstrItinClass; def IIC_LdStSTFDU : InstrItinClass;
def LdStSTVEBX : InstrItinClass; def IIC_LdStSTVEBX : InstrItinClass;
def LdStSTWCX : InstrItinClass; def IIC_LdStSTWCX : InstrItinClass;
def LdStSync : InstrItinClass; def IIC_LdStSync : InstrItinClass;
def SprISYNC : InstrItinClass; def IIC_SprISYNC : InstrItinClass;
def SprMFSR : InstrItinClass; def IIC_SprMFSR : InstrItinClass;
def SprMTMSR : InstrItinClass; def IIC_SprMTMSR : InstrItinClass;
def SprMTSR : InstrItinClass; def IIC_SprMTSR : InstrItinClass;
def SprTLBSYNC : InstrItinClass; def IIC_SprTLBSYNC : InstrItinClass;
def SprMFCR : InstrItinClass; def IIC_SprMFCR : InstrItinClass;
def SprMFMSR : InstrItinClass; def IIC_SprMFMSR : InstrItinClass;
def SprMFSPR : InstrItinClass; def IIC_SprMFSPR : InstrItinClass;
def SprMFTB : InstrItinClass; def IIC_SprMFTB : InstrItinClass;
def SprMTSPR : InstrItinClass; def IIC_SprMTSPR : InstrItinClass;
def SprMTSRIN : InstrItinClass; def IIC_SprMTSRIN : InstrItinClass;
def SprRFI : InstrItinClass; def IIC_SprRFI : InstrItinClass;
def SprSC : InstrItinClass; def IIC_SprSC : InstrItinClass;
def FPGeneral : InstrItinClass; def IIC_FPGeneral : InstrItinClass;
def FPAddSub : InstrItinClass; def IIC_FPAddSub : InstrItinClass;
def FPCompare : InstrItinClass; def IIC_FPCompare : InstrItinClass;
def FPDivD : InstrItinClass; def IIC_FPDivD : InstrItinClass;
def FPDivS : InstrItinClass; def IIC_FPDivS : InstrItinClass;
def FPFused : InstrItinClass; def IIC_FPFused : InstrItinClass;
def FPRes : InstrItinClass; def IIC_FPRes : InstrItinClass;
def FPSqrt : InstrItinClass; def IIC_FPSqrt : InstrItinClass;
def VecGeneral : InstrItinClass; def IIC_VecGeneral : InstrItinClass;
def VecFP : InstrItinClass; def IIC_VecFP : InstrItinClass;
def VecFPCompare : InstrItinClass; def IIC_VecFPCompare : InstrItinClass;
def VecComplex : InstrItinClass; def IIC_VecComplex : InstrItinClass;
def VecPerm : InstrItinClass; def IIC_VecPerm : InstrItinClass;
def VecFPRound : InstrItinClass; def IIC_VecFPRound : InstrItinClass;
def VecVSL : InstrItinClass; def IIC_VecVSL : InstrItinClass;
def VecVSR : InstrItinClass; def IIC_VecVSR : InstrItinClass;
def SprMTMSRD : InstrItinClass; def IIC_SprMTMSRD : InstrItinClass;
def SprSLIE : InstrItinClass; def IIC_SprSLIE : InstrItinClass;
def SprSLBIE : InstrItinClass; def IIC_SprSLBIE : InstrItinClass;
def SprSLBMTE : InstrItinClass; def IIC_SprSLBMTE : InstrItinClass;
def SprSLBMFEE : InstrItinClass; def IIC_SprSLBMFEE : InstrItinClass;
def SprSLBIA : InstrItinClass; def IIC_SprSLBIA : InstrItinClass;
def SprTLBIEL : InstrItinClass; def IIC_SprTLBIEL : InstrItinClass;
def SprTLBIE : InstrItinClass; def IIC_SprTLBIE : InstrItinClass;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Processor instruction itineraries. // Processor instruction itineraries.
@@ -136,392 +136,392 @@ include "PPCScheduleE5500.td"
// //
// opcode itinerary class // opcode itinerary class
// ====== =============== // ====== ===============
// add IntSimple // add IIC_IntSimple
// addc IntGeneral // addc IIC_IntGeneral
// adde IntGeneral // adde IIC_IntGeneral
// addi IntSimple // addi IIC_IntSimple
// addic IntGeneral // addic IIC_IntGeneral
// addic. IntGeneral // addic. IIC_IntGeneral
// addis IntSimple // addis IIC_IntSimple
// addme IntGeneral // addme IIC_IntGeneral
// addze IntGeneral // addze IIC_IntGeneral
// and IntSimple // and IIC_IntSimple
// andc IntSimple // andc IIC_IntSimple
// andi. IntGeneral // andi. IIC_IntGeneral
// andis. IntGeneral // andis. IIC_IntGeneral
// b BrB // b IIC_BrB
// bc BrB // bc IIC_BrB
// bcctr BrB // bcctr IIC_BrB
// bclr BrB // bclr IIC_BrB
// cmp IntCompare // cmp IIC_IntCompare
// cmpi IntCompare // cmpi IIC_IntCompare
// cmpl IntCompare // cmpl IIC_IntCompare
// cmpli IntCompare // cmpli IIC_IntCompare
// cntlzd IntRotateD // cntlzd IIC_IntRotateD
// cntlzw IntGeneral // cntlzw IIC_IntGeneral
// crand BrCR // crand IIC_BrCR
// crandc BrCR // crandc IIC_BrCR
// creqv BrCR // creqv IIC_BrCR
// crnand BrCR // crnand IIC_BrCR
// crnor BrCR // crnor IIC_BrCR
// cror BrCR // cror IIC_BrCR
// crorc BrCR // crorc IIC_BrCR
// crxor BrCR // crxor IIC_BrCR
// dcba LdStDCBA // dcba IIC_LdStDCBA
// dcbf LdStDCBF // dcbf IIC_LdStDCBF
// dcbi LdStDCBI // dcbi IIC_LdStDCBI
// dcbst LdStDCBF // dcbst IIC_LdStDCBF
// dcbt LdStLoad // dcbt IIC_LdStLoad
// dcbtst LdStLoad // dcbtst IIC_LdStLoad
// dcbz LdStDCBF // dcbz IIC_LdStDCBF
// divd IntDivD // divd IIC_IntDivD
// divdu IntDivD // divdu IIC_IntDivD
// divw IntDivW // divw IIC_IntDivW
// divwu IntDivW // divwu IIC_IntDivW
// dss LdStDSS // dss IIC_LdStDSS
// dst LdStDSS // dst IIC_LdStDSS
// dstst LdStDSS // dstst IIC_LdStDSS
// eciwx LdStLoad // eciwx IIC_LdStLoad
// ecowx LdStLoad // ecowx IIC_LdStLoad
// eieio LdStLoad // eieio IIC_LdStLoad
// eqv IntSimple // eqv IIC_IntSimple
// extsb IntSimple // extsb IIC_IntSimple
// extsh IntSimple // extsh IIC_IntSimple
// extsw IntSimple // extsw IIC_IntSimple
// fabs FPGeneral // fabs IIC_FPGeneral
// fadd FPAddSub // fadd IIC_FPAddSub
// fadds FPGeneral // fadds IIC_FPGeneral
// fcfid FPGeneral // fcfid IIC_FPGeneral
// fcmpo FPCompare // fcmpo IIC_FPCompare
// fcmpu FPCompare // fcmpu IIC_FPCompare
// fctid FPGeneral // fctid IIC_FPGeneral
// fctidz FPGeneral // fctidz IIC_FPGeneral
// fctiw FPGeneral // fctiw IIC_FPGeneral
// fctiwz FPGeneral // fctiwz IIC_FPGeneral
// fdiv FPDivD // fdiv IIC_FPDivD
// fdivs FPDivS // fdivs IIC_FPDivS
// fmadd FPFused // fmadd IIC_FPFused
// fmadds FPGeneral // fmadds IIC_FPGeneral
// fmr FPGeneral // fmr IIC_FPGeneral
// fmsub FPFused // fmsub IIC_FPFused
// fmsubs FPGeneral // fmsubs IIC_FPGeneral
// fmul FPFused // fmul IIC_FPFused
// fmuls FPGeneral // fmuls IIC_FPGeneral
// fnabs FPGeneral // fnabs IIC_FPGeneral
// fneg FPGeneral // fneg IIC_FPGeneral
// fnmadd FPFused // fnmadd IIC_FPFused
// fnmadds FPGeneral // fnmadds IIC_FPGeneral
// fnmsub FPFused // fnmsub IIC_FPFused
// fnmsubs FPGeneral // fnmsubs IIC_FPGeneral
// fres FPRes // fres IIC_FPRes
// frsp FPGeneral // frsp IIC_FPGeneral
// frsqrte FPGeneral // frsqrte IIC_FPGeneral
// fsel FPGeneral // fsel IIC_FPGeneral
// fsqrt FPSqrt // fsqrt IIC_FPSqrt
// fsqrts FPSqrt // fsqrts IIC_FPSqrt
// fsub FPAddSub // fsub IIC_FPAddSub
// fsubs FPGeneral // fsubs IIC_FPGeneral
// icbi LdStICBI // icbi IIC_LdStICBI
// isync SprISYNC // isync IIC_SprISYNC
// lbz LdStLoad // lbz IIC_LdStLoad
// lbzu LdStLoadUpd // lbzu IIC_LdStLoadUpd
// lbzux LdStLoadUpd // lbzux IIC_LdStLoadUpd
// lbzx LdStLoad // lbzx IIC_LdStLoad
// ld LdStLD // ld IIC_LdStLD
// ldarx LdStLDARX // ldarx IIC_LdStLDARX
// ldu LdStLDU // ldu IIC_LdStLDU
// ldux LdStLDU // ldux IIC_LdStLDU
// ldx LdStLD // ldx IIC_LdStLD
// lfd LdStLFD // lfd IIC_LdStLFD
// lfdu LdStLFDU // lfdu IIC_LdStLFDU
// lfdux LdStLFDU // lfdux IIC_LdStLFDU
// lfdx LdStLFD // lfdx IIC_LdStLFD
// lfs LdStLFD // lfs IIC_LdStLFD
// lfsu LdStLFDU // lfsu IIC_LdStLFDU
// lfsux LdStLFDU // lfsux IIC_LdStLFDU
// lfsx LdStLFD // lfsx IIC_LdStLFD
// lha LdStLHA // lha IIC_LdStLHA
// lhau LdStLHAU // lhau IIC_LdStLHAU
// lhaux LdStLHAU // lhaux IIC_LdStLHAU
// lhax LdStLHA // lhax IIC_LdStLHA
// lhbrx LdStLoad // lhbrx IIC_LdStLoad
// lhz LdStLoad // lhz IIC_LdStLoad
// lhzu LdStLoadUpd // lhzu IIC_LdStLoadUpd
// lhzux LdStLoadUpd // lhzux IIC_LdStLoadUpd
// lhzx LdStLoad // lhzx IIC_LdStLoad
// lmw LdStLMW // lmw IIC_LdStLMW
// lswi LdStLMW // lswi IIC_LdStLMW
// lswx LdStLMW // lswx IIC_LdStLMW
// lvebx LdStLVecX // lvebx IIC_LdStLVecX
// lvehx LdStLVecX // lvehx IIC_LdStLVecX
// lvewx LdStLVecX // lvewx IIC_LdStLVecX
// lvsl LdStLVecX // lvsl IIC_LdStLVecX
// lvsr LdStLVecX // lvsr IIC_LdStLVecX
// lvx LdStLVecX // lvx IIC_LdStLVecX
// lvxl LdStLVecX // lvxl IIC_LdStLVecX
// lwa LdStLWA // lwa IIC_LdStLWA
// lwarx LdStLWARX // lwarx IIC_LdStLWARX
// lwaux LdStLHAU // lwaux IIC_LdStLHAU
// lwax LdStLHA // lwax IIC_LdStLHA
// lwbrx LdStLoad // lwbrx IIC_LdStLoad
// lwz LdStLoad // lwz IIC_LdStLoad
// lwzu LdStLoadUpd // lwzu IIC_LdStLoadUpd
// lwzux LdStLoadUpd // lwzux IIC_LdStLoadUpd
// lwzx LdStLoad // lwzx IIC_LdStLoad
// mcrf BrMCR // mcrf IIC_BrMCR
// mcrfs FPGeneral // mcrfs IIC_FPGeneral
// mcrxr BrMCRX // mcrxr IIC_BrMCRX
// mfcr SprMFCR // mfcr IIC_SprMFCR
// mffs IntMFFS // mffs IIC_IntMFFS
// mfmsr SprMFMSR // mfmsr IIC_SprMFMSR
// mfspr SprMFSPR // mfspr IIC_SprMFSPR
// mfsr SprMFSR // mfsr IIC_SprMFSR
// mfsrin SprMFSR // mfsrin IIC_SprMFSR
// mftb SprMFTB // mftb IIC_SprMFTB
// mfvscr IntMFVSCR // mfvscr IIC_IntMFVSCR
// mtcrf BrMCRX // mtcrf IIC_BrMCRX
// mtfsb0 IntMTFSB0 // mtfsb0 IIC_IntMTFSB0
// mtfsb1 IntMTFSB0 // mtfsb1 IIC_IntMTFSB0
// mtfsf IntMTFSB0 // mtfsf IIC_IntMTFSB0
// mtfsfi IntMTFSB0 // mtfsfi IIC_IntMTFSB0
// mtmsr SprMTMSR // mtmsr IIC_SprMTMSR
// mtmsrd LdStLD // mtmsrd IIC_LdStLD
// mtspr SprMTSPR // mtspr IIC_SprMTSPR
// mtsr SprMTSR // mtsr IIC_SprMTSR
// mtsrd IntMTSRD // mtsrd IIC_IntMTSRD
// mtsrdin IntMTSRD // mtsrdin IIC_IntMTSRD
// mtsrin SprMTSRIN // mtsrin IIC_SprMTSRIN
// mtvscr IntMFVSCR // mtvscr IIC_IntMFVSCR
// mulhd IntMulHD // mulhd IIC_IntMulHD
// mulhdu IntMulHD // mulhdu IIC_IntMulHD
// mulhw IntMulHW // mulhw IIC_IntMulHW
// mulhwu IntMulHWU // mulhwu IIC_IntMulHWU
// mulld IntMulHD // mulld IIC_IntMulHD
// mulli IntMulLI // mulli IIC_IntMulLI
// mullw IntMulHW // mullw IIC_IntMulHW
// nand IntSimple // nand IIC_IntSimple
// neg IntSimple // neg IIC_IntSimple
// nor IntSimple // nor IIC_IntSimple
// or IntSimple // or IIC_IntSimple
// orc IntSimple // orc IIC_IntSimple
// ori IntSimple // ori IIC_IntSimple
// oris IntSimple // oris IIC_IntSimple
// rfi SprRFI // rfi IIC_SprRFI
// rfid IntRFID // rfid IIC_IntRFID
// rldcl IntRotateD // rldcl IIC_IntRotateD
// rldcr IntRotateD // rldcr IIC_IntRotateD
// rldic IntRotateDI // rldic IIC_IntRotateDI
// rldicl IntRotateDI // rldicl IIC_IntRotateDI
// rldicr IntRotateDI // rldicr IIC_IntRotateDI
// rldimi IntRotateDI // rldimi IIC_IntRotateDI
// rlwimi IntRotate // rlwimi IIC_IntRotate
// rlwinm IntGeneral // rlwinm IIC_IntGeneral
// rlwnm IntGeneral // rlwnm IIC_IntGeneral
// sc SprSC // sc IIC_SprSC
// slbia LdStSLBIA // slbia IIC_LdStSLBIA
// slbie LdStSLBIE // slbie IIC_LdStSLBIE
// sld IntRotateD // sld IIC_IntRotateD
// slw IntGeneral // slw IIC_IntGeneral
// srad IntRotateD // srad IIC_IntRotateD
// sradi IntRotateDI // sradi IIC_IntRotateDI
// sraw IntShift // sraw IIC_IntShift
// srawi IntShift // srawi IIC_IntShift
// srd IntRotateD // srd IIC_IntRotateD
// srw IntGeneral // srw IIC_IntGeneral
// stb LdStStore // stb IIC_LdStStore
// stbu LdStStoreUpd // stbu IIC_LdStStoreUpd
// stbux LdStStoreUpd // stbux IIC_LdStStoreUpd
// stbx LdStStore // stbx IIC_LdStStore
// std LdStSTD // std IIC_LdStSTD
// stdcx. LdStSTDCX // stdcx. IIC_LdStSTDCX
// stdu LdStSTDU // stdu IIC_LdStSTDU
// stdux LdStSTDU // stdux IIC_LdStSTDU
// stdx LdStSTD // stdx IIC_LdStSTD
// stfd LdStSTFD // stfd IIC_LdStSTFD
// stfdu LdStSTFDU // stfdu IIC_LdStSTFDU
// stfdux LdStSTFDU // stfdux IIC_LdStSTFDU
// stfdx LdStSTFD // stfdx IIC_LdStSTFD
// stfiwx LdStSTFD // stfiwx IIC_LdStSTFD
// stfs LdStSTFD // stfs IIC_LdStSTFD
// stfsu LdStSTFDU // stfsu IIC_LdStSTFDU
// stfsux LdStSTFDU // stfsux IIC_LdStSTFDU
// stfsx LdStSTFD // stfsx IIC_LdStSTFD
// sth LdStStore // sth IIC_LdStStore
// sthbrx LdStStore // sthbrx IIC_LdStStore
// sthu LdStStoreUpd // sthu IIC_LdStStoreUpd
// sthux LdStStoreUpd // sthux IIC_LdStStoreUpd
// sthx LdStStore // sthx IIC_LdStStore
// stmw LdStLMW // stmw IIC_LdStLMW
// stswi LdStLMW // stswi IIC_LdStLMW
// stswx LdStLMW // stswx IIC_LdStLMW
// stvebx LdStSTVEBX // stvebx IIC_LdStSTVEBX
// stvehx LdStSTVEBX // stvehx IIC_LdStSTVEBX
// stvewx LdStSTVEBX // stvewx IIC_LdStSTVEBX
// stvx LdStSTVEBX // stvx IIC_LdStSTVEBX
// stvxl LdStSTVEBX // stvxl IIC_LdStSTVEBX
// stw LdStStore // stw IIC_LdStStore
// stwbrx LdStStore // stwbrx IIC_LdStStore
// stwcx. LdStSTWCX // stwcx. IIC_LdStSTWCX
// stwu LdStStoreUpd // stwu IIC_LdStStoreUpd
// stwux LdStStoreUpd // stwux IIC_LdStStoreUpd
// stwx LdStStore // stwx IIC_LdStStore
// subf IntGeneral // subf IIC_IntGeneral
// subfc IntGeneral // subfc IIC_IntGeneral
// subfe IntGeneral // subfe IIC_IntGeneral
// subfic IntGeneral // subfic IIC_IntGeneral
// subfme IntGeneral // subfme IIC_IntGeneral
// subfze IntGeneral // subfze IIC_IntGeneral
// sync LdStSync // sync IIC_LdStSync
// td IntTrapD // td IIC_IntTrapD
// tdi IntTrapD // tdi IIC_IntTrapD
// tlbia LdStSLBIA // tlbia IIC_LdStSLBIA
// tlbie LdStDCBF // tlbie IIC_LdStDCBF
// tlbsync SprTLBSYNC // tlbsync IIC_SprTLBSYNC
// tw IntTrapW // tw IIC_IntTrapW
// twi IntTrapW // twi IIC_IntTrapW
// vaddcuw VecGeneral // vaddcuw IIC_VecGeneral
// vaddfp VecFP // vaddfp IIC_VecFP
// vaddsbs VecGeneral // vaddsbs IIC_VecGeneral
// vaddshs VecGeneral // vaddshs IIC_VecGeneral
// vaddsws VecGeneral // vaddsws IIC_VecGeneral
// vaddubm VecGeneral // vaddubm IIC_VecGeneral
// vaddubs VecGeneral // vaddubs IIC_VecGeneral
// vadduhm VecGeneral // vadduhm IIC_VecGeneral
// vadduhs VecGeneral // vadduhs IIC_VecGeneral
// vadduwm VecGeneral // vadduwm IIC_VecGeneral
// vadduws VecGeneral // vadduws IIC_VecGeneral
// vand VecGeneral // vand IIC_VecGeneral
// vandc VecGeneral // vandc IIC_VecGeneral
// vavgsb VecGeneral // vavgsb IIC_VecGeneral
// vavgsh VecGeneral // vavgsh IIC_VecGeneral
// vavgsw VecGeneral // vavgsw IIC_VecGeneral
// vavgub VecGeneral // vavgub IIC_VecGeneral
// vavguh VecGeneral // vavguh IIC_VecGeneral
// vavguw VecGeneral // vavguw IIC_VecGeneral
// vcfsx VecFP // vcfsx IIC_VecFP
// vcfux VecFP // vcfux IIC_VecFP
// vcmpbfp VecFPCompare // vcmpbfp IIC_VecFPCompare
// vcmpeqfp VecFPCompare // vcmpeqfp IIC_VecFPCompare
// vcmpequb VecGeneral // vcmpequb IIC_VecGeneral
// vcmpequh VecGeneral // vcmpequh IIC_VecGeneral
// vcmpequw VecGeneral // vcmpequw IIC_VecGeneral
// vcmpgefp VecFPCompare // vcmpgefp IIC_VecFPCompare
// vcmpgtfp VecFPCompare // vcmpgtfp IIC_VecFPCompare
// vcmpgtsb VecGeneral // vcmpgtsb IIC_VecGeneral
// vcmpgtsh VecGeneral // vcmpgtsh IIC_VecGeneral
// vcmpgtsw VecGeneral // vcmpgtsw IIC_VecGeneral
// vcmpgtub VecGeneral // vcmpgtub IIC_VecGeneral
// vcmpgtuh VecGeneral // vcmpgtuh IIC_VecGeneral
// vcmpgtuw VecGeneral // vcmpgtuw IIC_VecGeneral
// vctsxs VecFP // vctsxs IIC_VecFP
// vctuxs VecFP // vctuxs IIC_VecFP
// vexptefp VecFP // vexptefp IIC_VecFP
// vlogefp VecFP // vlogefp IIC_VecFP
// vmaddfp VecFP // vmaddfp IIC_VecFP
// vmaxfp VecFPCompare // vmaxfp IIC_VecFPCompare
// vmaxsb VecGeneral // vmaxsb IIC_VecGeneral
// vmaxsh VecGeneral // vmaxsh IIC_VecGeneral
// vmaxsw VecGeneral // vmaxsw IIC_VecGeneral
// vmaxub VecGeneral // vmaxub IIC_VecGeneral
// vmaxuh VecGeneral // vmaxuh IIC_VecGeneral
// vmaxuw VecGeneral // vmaxuw IIC_VecGeneral
// vmhaddshs VecComplex // vmhaddshs IIC_VecComplex
// vmhraddshs VecComplex // vmhraddshs IIC_VecComplex
// vminfp VecFPCompare // vminfp IIC_VecFPCompare
// vminsb VecGeneral // vminsb IIC_VecGeneral
// vminsh VecGeneral // vminsh IIC_VecGeneral
// vminsw VecGeneral // vminsw IIC_VecGeneral
// vminub VecGeneral // vminub IIC_VecGeneral
// vminuh VecGeneral // vminuh IIC_VecGeneral
// vminuw VecGeneral // vminuw IIC_VecGeneral
// vmladduhm VecComplex // vmladduhm IIC_VecComplex
// vmrghb VecPerm // vmrghb IIC_VecPerm
// vmrghh VecPerm // vmrghh IIC_VecPerm
// vmrghw VecPerm // vmrghw IIC_VecPerm
// vmrglb VecPerm // vmrglb IIC_VecPerm
// vmrglh VecPerm // vmrglh IIC_VecPerm
// vmrglw VecPerm // vmrglw IIC_VecPerm
// vmsubfp VecFP // vmsubfp IIC_VecFP
// vmsummbm VecComplex // vmsummbm IIC_VecComplex
// vmsumshm VecComplex // vmsumshm IIC_VecComplex
// vmsumshs VecComplex // vmsumshs IIC_VecComplex
// vmsumubm VecComplex // vmsumubm IIC_VecComplex
// vmsumuhm VecComplex // vmsumuhm IIC_VecComplex
// vmsumuhs VecComplex // vmsumuhs IIC_VecComplex
// vmulesb VecComplex // vmulesb IIC_VecComplex
// vmulesh VecComplex // vmulesh IIC_VecComplex
// vmuleub VecComplex // vmuleub IIC_VecComplex
// vmuleuh VecComplex // vmuleuh IIC_VecComplex
// vmulosb VecComplex // vmulosb IIC_VecComplex
// vmulosh VecComplex // vmulosh IIC_VecComplex
// vmuloub VecComplex // vmuloub IIC_VecComplex
// vmulouh VecComplex // vmulouh IIC_VecComplex
// vnor VecGeneral // vnor IIC_VecGeneral
// vor VecGeneral // vor IIC_VecGeneral
// vperm VecPerm // vperm IIC_VecPerm
// vpkpx VecPerm // vpkpx IIC_VecPerm
// vpkshss VecPerm // vpkshss IIC_VecPerm
// vpkshus VecPerm // vpkshus IIC_VecPerm
// vpkswss VecPerm // vpkswss IIC_VecPerm
// vpkswus VecPerm // vpkswus IIC_VecPerm
// vpkuhum VecPerm // vpkuhum IIC_VecPerm
// vpkuhus VecPerm // vpkuhus IIC_VecPerm
// vpkuwum VecPerm // vpkuwum IIC_VecPerm
// vpkuwus VecPerm // vpkuwus IIC_VecPerm
// vrefp VecFPRound // vrefp IIC_VecFPRound
// vrfim VecFPRound // vrfim IIC_VecFPRound
// vrfin VecFPRound // vrfin IIC_VecFPRound
// vrfip VecFPRound // vrfip IIC_VecFPRound
// vrfiz VecFPRound // vrfiz IIC_VecFPRound
// vrlb VecGeneral // vrlb IIC_VecGeneral
// vrlh VecGeneral // vrlh IIC_VecGeneral
// vrlw VecGeneral // vrlw IIC_VecGeneral
// vrsqrtefp VecFP // vrsqrtefp IIC_VecFP
// vsel VecGeneral // vsel IIC_VecGeneral
// vsl VecVSL // vsl IIC_VecVSL
// vslb VecGeneral // vslb IIC_VecGeneral
// vsldoi VecPerm // vsldoi IIC_VecPerm
// vslh VecGeneral // vslh IIC_VecGeneral
// vslo VecPerm // vslo IIC_VecPerm
// vslw VecGeneral // vslw IIC_VecGeneral
// vspltb VecPerm // vspltb IIC_VecPerm
// vsplth VecPerm // vsplth IIC_VecPerm
// vspltisb VecPerm // vspltisb IIC_VecPerm
// vspltish VecPerm // vspltish IIC_VecPerm
// vspltisw VecPerm // vspltisw IIC_VecPerm
// vspltw VecPerm // vspltw IIC_VecPerm
// vsr VecVSR // vsr IIC_VecVSR
// vsrab VecGeneral // vsrab IIC_VecGeneral
// vsrah VecGeneral // vsrah IIC_VecGeneral
// vsraw VecGeneral // vsraw IIC_VecGeneral
// vsrb VecGeneral // vsrb IIC_VecGeneral
// vsrh VecGeneral // vsrh IIC_VecGeneral
// vsro VecPerm // vsro IIC_VecPerm
// vsrw VecGeneral // vsrw IIC_VecGeneral
// vsubcuw VecGeneral // vsubcuw IIC_VecGeneral
// vsubfp VecFP // vsubfp IIC_VecFP
// vsubsbs VecGeneral // vsubsbs IIC_VecGeneral
// vsubshs VecGeneral // vsubshs IIC_VecGeneral
// vsubsws VecGeneral // vsubsws IIC_VecGeneral
// vsububm VecGeneral // vsububm IIC_VecGeneral
// vsububs VecGeneral // vsububs IIC_VecGeneral
// vsubuhm VecGeneral // vsubuhm IIC_VecGeneral
// vsubuhs VecGeneral // vsubuhs IIC_VecGeneral
// vsubuwm VecGeneral // vsubuwm IIC_VecGeneral
// vsubuws VecGeneral // vsubuws IIC_VecGeneral
// vsum2sws VecComplex // vsum2sws IIC_VecComplex
// vsum4sbs VecComplex // vsum4sbs IIC_VecComplex
// vsum4shs VecComplex // vsum4shs IIC_VecComplex
// vsum4ubs VecComplex // vsum4ubs IIC_VecComplex
// vsumsws VecComplex // vsumsws IIC_VecComplex
// vupkhpx VecPerm // vupkhpx IIC_VecPerm
// vupkhsb VecPerm // vupkhsb IIC_VecPerm
// vupkhsh VecPerm // vupkhsh IIC_VecPerm
// vupklpx VecPerm // vupklpx IIC_VecPerm
// vupklsb VecPerm // vupklsb IIC_VecPerm
// vupklsh VecPerm // vupklsh IIC_VecPerm
// vxor VecGeneral // vxor IIC_VecGeneral
// xor IntSimple // xor IIC_IntSimple
// xori IntSimple // xori IIC_IntSimple
// xoris IntSimple // xoris IIC_IntSimple
// //

114
lib/Target/PowerPC/PPCSchedule440.td
View File

@@ -108,7 +108,7 @@ def PPC440Itineraries : ProcessorItineraries<
IRACC, IEXE1, IEXE2, IWB, LRACC, JEXE1, JEXE2, JWB, AGEN, CRD, LWB, IRACC, IEXE1, IEXE2, IWB, LRACC, JEXE1, JEXE2, JWB, AGEN, CRD, LWB,
FEXE1, FEXE2, FEXE3, FEXE4, FEXE5, FEXE6, FWB, LWARX_Hold], FEXE1, FEXE2, FEXE3, FEXE4, FEXE5, FEXE6, FWB, LWARX_Hold],
[GPR_Bypass, FPR_Bypass], [ [GPR_Bypass, FPR_Bypass], [
InstrItinData<IntSimple , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_IntSimple, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [IRACC, LRACC]>, InstrStage<1, [IRACC, LRACC]>,
@@ -117,7 +117,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [IWB, JWB]>], InstrStage<1, [IWB, JWB]>],
[6, 4, 4], [6, 4, 4],
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntGeneral , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_IntGeneral, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [IRACC, LRACC]>, InstrStage<1, [IRACC, LRACC]>,
@@ -126,7 +126,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [IWB, JWB]>], InstrStage<1, [IWB, JWB]>],
[6, 4, 4], [6, 4, 4],
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntCompare , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_IntCompare, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [IRACC, LRACC]>, InstrStage<1, [IRACC, LRACC]>,
@@ -135,7 +135,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [IWB, JWB]>], InstrStage<1, [IWB, JWB]>],
[6, 4, 4], [6, 4, 4],
[NoBypass, GPR_Bypass, GPR_Bypass]>, [NoBypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntDivW , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_IntDivW, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [IRACC]>, InstrStage<1, [IRACC]>,
@@ -144,7 +144,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<33, [IWB]>], InstrStage<33, [IWB]>],
[40, 4, 4], [40, 4, 4],
[NoBypass, GPR_Bypass, GPR_Bypass]>, [NoBypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntMFFS , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_IntMFFS, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [IRACC]>, InstrStage<1, [IRACC]>,
@@ -153,7 +153,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [IWB]>], InstrStage<1, [IWB]>],
[7, 4, 4], [7, 4, 4],
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntMTFSB0 , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [IRACC]>, InstrStage<1, [IRACC]>,
@@ -162,7 +162,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [IWB]>], InstrStage<1, [IWB]>],
[7, 4, 4], [7, 4, 4],
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntMulHW , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_IntMulHW, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [IRACC]>, InstrStage<1, [IRACC]>,
@@ -171,7 +171,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [IWB]>], InstrStage<1, [IWB]>],
[8, 4, 4], [8, 4, 4],
[NoBypass, GPR_Bypass, GPR_Bypass]>, [NoBypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntMulHWU , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_IntMulHWU, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [IRACC]>, InstrStage<1, [IRACC]>,
@@ -180,7 +180,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [IWB]>], InstrStage<1, [IWB]>],
[8, 4, 4], [8, 4, 4],
[NoBypass, GPR_Bypass, GPR_Bypass]>, [NoBypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntMulLI , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_IntMulLI, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [IRACC]>, InstrStage<1, [IRACC]>,
@@ -189,7 +189,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [IWB]>], InstrStage<1, [IWB]>],
[8, 4, 4], [8, 4, 4],
[NoBypass, GPR_Bypass, GPR_Bypass]>, [NoBypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntRotate , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_IntRotate, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [IRACC, LRACC]>, InstrStage<1, [IRACC, LRACC]>,
@@ -198,7 +198,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [IWB, JWB]>], InstrStage<1, [IWB, JWB]>],
[6, 4, 4], [6, 4, 4],
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntShift , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_IntShift, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [IRACC, LRACC]>, InstrStage<1, [IRACC, LRACC]>,
@@ -207,7 +207,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [IWB, JWB]>], InstrStage<1, [IWB, JWB]>],
[6, 4, 4], [6, 4, 4],
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntTrapW , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_IntTrapW, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [IRACC]>, InstrStage<1, [IRACC]>,
@@ -216,7 +216,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [IWB]>], InstrStage<1, [IWB]>],
[6, 4], [6, 4],
[GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass]>,
InstrItinData<BrB , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_BrB, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [IRACC]>, InstrStage<1, [IRACC]>,
@@ -225,7 +225,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [IWB]>], InstrStage<1, [IWB]>],
[8, 4], [8, 4],
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<BrCR , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_BrCR, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [IRACC]>, InstrStage<1, [IRACC]>,
@@ -234,7 +234,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [IWB]>], InstrStage<1, [IWB]>],
[8, 4, 4], [8, 4, 4],
[NoBypass, GPR_Bypass, GPR_Bypass]>, [NoBypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<BrMCR , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_BrMCR, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [IRACC]>, InstrStage<1, [IRACC]>,
@@ -243,7 +243,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [IWB]>], InstrStage<1, [IWB]>],
[8, 4, 4], [8, 4, 4],
[NoBypass, GPR_Bypass, GPR_Bypass]>, [NoBypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<BrMCRX , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_BrMCRX, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [IRACC]>, InstrStage<1, [IRACC]>,
@@ -252,7 +252,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [IWB]>], InstrStage<1, [IWB]>],
[8, 4, 4], [8, 4, 4],
[NoBypass, GPR_Bypass, GPR_Bypass]>, [NoBypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<LdStDCBA , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_LdStDCBA, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [LRACC]>, InstrStage<1, [LRACC]>,
@@ -261,7 +261,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [LWB]>], InstrStage<1, [LWB]>],
[8, 5], [8, 5],
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<LdStDCBF , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_LdStDCBF, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [LRACC]>, InstrStage<1, [LRACC]>,
@@ -270,7 +270,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [LWB]>], InstrStage<1, [LWB]>],
[8, 5], [8, 5],
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<LdStDCBI , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_LdStDCBI, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [LRACC]>, InstrStage<1, [LRACC]>,
@@ -279,7 +279,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [LWB]>], InstrStage<1, [LWB]>],
[8, 5], [8, 5],
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<LdStLoad , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_LdStLoad, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [LRACC]>, InstrStage<1, [LRACC]>,
@@ -288,7 +288,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<2, [LWB]>], InstrStage<2, [LWB]>],
[9, 5], [9, 5],
[GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass]>,
InstrItinData<LdStLoadUpd , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_LdStLoadUpd,[InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [LRACC]>, InstrStage<1, [LRACC]>,
@@ -297,7 +297,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<2, [LWB]>], InstrStage<2, [LWB]>],
[9, 5], [9, 5],
[GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass]>,
InstrItinData<LdStStore , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_LdStStore, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [LRACC]>, InstrStage<1, [LRACC]>,
@@ -306,7 +306,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<2, [LWB]>], InstrStage<2, [LWB]>],
[8, 5], [8, 5],
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<LdStStoreUpd, [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [LRACC]>, InstrStage<1, [LRACC]>,
@@ -315,7 +315,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<2, [LWB]>], InstrStage<2, [LWB]>],
[8, 5], [8, 5],
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<LdStICBI , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_LdStICBI, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [LRACC]>, InstrStage<1, [LRACC]>,
@@ -324,7 +324,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [LWB]>], InstrStage<1, [LWB]>],
[8, 5], [8, 5],
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<LdStSTFD , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_LdStSTFD, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [LRACC]>, InstrStage<1, [LRACC]>,
@@ -333,7 +333,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [LWB]>], InstrStage<1, [LWB]>],
[8, 5, 5], [8, 5, 5],
[NoBypass, GPR_Bypass, GPR_Bypass]>, [NoBypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<LdStSTFDU , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [LRACC]>, InstrStage<1, [LRACC]>,
@@ -342,7 +342,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [LWB]>], InstrStage<1, [LWB]>],
[8, 5, 5], [8, 5, 5],
[NoBypass, GPR_Bypass, GPR_Bypass]>, [NoBypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<LdStLFD , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_LdStLFD, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [LRACC]>, InstrStage<1, [LRACC]>,
@@ -351,7 +351,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<2, [LWB]>], InstrStage<2, [LWB]>],
[9, 5, 5], [9, 5, 5],
[NoBypass, GPR_Bypass, GPR_Bypass]>, [NoBypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<LdStLFDU , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_LdStLFDU, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [LRACC]>, InstrStage<1, [LRACC]>,
@@ -360,7 +360,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [LWB]>], InstrStage<1, [LWB]>],
[9, 5, 5], [9, 5, 5],
[NoBypass, GPR_Bypass, GPR_Bypass]>, [NoBypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<LdStLHA , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_LdStLHA, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [LRACC]>, InstrStage<1, [LRACC]>,
@@ -369,7 +369,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [LWB]>], InstrStage<1, [LWB]>],
[8, 5], [8, 5],
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<LdStLHAU , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_LdStLHAU, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [LRACC]>, InstrStage<1, [LRACC]>,
@@ -378,7 +378,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [LWB]>], InstrStage<1, [LWB]>],
[8, 5], [8, 5],
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<LdStLMW , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_LdStLMW, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [LRACC]>, InstrStage<1, [LRACC]>,
@@ -387,7 +387,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [LWB]>], InstrStage<1, [LWB]>],
[8, 5], [8, 5],
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<LdStLWARX , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_LdStLWARX, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1]>, InstrStage<1, [DISS1]>,
InstrStage<1, [IRACC], 0>, InstrStage<1, [IRACC], 0>,
@@ -398,7 +398,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [LWB]>], InstrStage<1, [LWB]>],
[8, 5], [8, 5],
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<LdStSTD , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_LdStSTD, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [LRACC]>, InstrStage<1, [LRACC]>,
@@ -407,7 +407,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<2, [LWB]>], InstrStage<2, [LWB]>],
[8, 5], [8, 5],
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<LdStSTDU , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_LdStSTDU, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [LRACC]>, InstrStage<1, [LRACC]>,
@@ -416,7 +416,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<2, [LWB]>], InstrStage<2, [LWB]>],
[8, 5], [8, 5],
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<LdStSTDCX , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1]>, InstrStage<1, [DISS1]>,
InstrStage<1, [IRACC], 0>, InstrStage<1, [IRACC], 0>,
@@ -427,7 +427,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [LWB]>], InstrStage<1, [LWB]>],
[8, 5], [8, 5],
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<LdStSTWCX , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1]>, InstrStage<1, [DISS1]>,
InstrStage<1, [IRACC], 0>, InstrStage<1, [IRACC], 0>,
@@ -438,14 +438,14 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [LWB]>], InstrStage<1, [LWB]>],
[8, 5], [8, 5],
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<LdStSync , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_LdStSync, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [LRACC]>, InstrStage<1, [LRACC]>,
InstrStage<3, [AGEN], 1>, InstrStage<3, [AGEN], 1>,
InstrStage<2, [CRD], 1>, InstrStage<2, [CRD], 1>,
InstrStage<1, [LWB]>]>, InstrStage<1, [LWB]>]>,
InstrItinData<SprISYNC , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_SprISYNC, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [FRACC], 0>, InstrStage<1, [FRACC], 0>,
@@ -463,7 +463,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<6, [LWB], 0>, InstrStage<6, [LWB], 0>,
InstrStage<6, [JWB], 0>, InstrStage<6, [JWB], 0>,
InstrStage<6, [IWB]>]>, InstrStage<6, [IWB]>]>,
InstrItinData<SprMFSR , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_SprMFSR, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [IRACC]>, InstrStage<1, [IRACC]>,
@@ -472,7 +472,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [IWB]>], InstrStage<1, [IWB]>],
[6, 4], [6, 4],
[GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass]>,
InstrItinData<SprMTMSR , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_SprMTMSR, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [IRACC]>, InstrStage<1, [IRACC]>,
@@ -481,7 +481,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [IWB]>], InstrStage<1, [IWB]>],
[6, 4], [6, 4],
[GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass]>,
InstrItinData<SprMTSR , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_SprMTSR, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [IRACC]>, InstrStage<1, [IRACC]>,
@@ -490,14 +490,14 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<3, [IWB]>], InstrStage<3, [IWB]>],
[9, 4], [9, 4],
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<SprTLBSYNC , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [IRACC]>, InstrStage<1, [IRACC]>,
InstrStage<1, [IEXE1]>, InstrStage<1, [IEXE1]>,
InstrStage<1, [IEXE2]>, InstrStage<1, [IEXE2]>,
InstrStage<1, [IWB]>]>, InstrStage<1, [IWB]>]>,
InstrItinData<SprMFCR , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_SprMFCR, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [IRACC]>, InstrStage<1, [IRACC]>,
@@ -506,7 +506,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [IWB]>], InstrStage<1, [IWB]>],
[8, 4], [8, 4],
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<SprMFMSR , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_SprMFMSR, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [IRACC]>, InstrStage<1, [IRACC]>,
@@ -515,7 +515,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [IWB]>], InstrStage<1, [IWB]>],
[7, 4], [7, 4],
[GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass]>,
InstrItinData<SprMFSPR , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_SprMFSPR, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [IRACC]>, InstrStage<1, [IRACC]>,
@@ -524,7 +524,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<3, [IWB]>], InstrStage<3, [IWB]>],
[10, 4], [10, 4],
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<SprMFTB , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_SprMFTB, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [IRACC]>, InstrStage<1, [IRACC]>,
@@ -533,7 +533,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<3, [IWB]>], InstrStage<3, [IWB]>],
[10, 4], [10, 4],
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<SprMTSPR , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_SprMTSPR, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [IRACC]>, InstrStage<1, [IRACC]>,
@@ -542,7 +542,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<3, [IWB]>], InstrStage<3, [IWB]>],
[10, 4], [10, 4],
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<SprMTSRIN , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [IRACC]>, InstrStage<1, [IRACC]>,
@@ -551,7 +551,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<3, [IWB]>], InstrStage<3, [IWB]>],
[10, 4], [10, 4],
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<SprRFI , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_SprRFI, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [IRACC]>, InstrStage<1, [IRACC]>,
@@ -560,7 +560,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [IWB]>], InstrStage<1, [IWB]>],
[8, 4], [8, 4],
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<SprSC , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_SprSC, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [IRACC]>, InstrStage<1, [IRACC]>,
@@ -569,7 +569,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [IWB]>], InstrStage<1, [IWB]>],
[8, 4], [8, 4],
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<FPGeneral , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_FPGeneral, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [FRACC]>, InstrStage<1, [FRACC]>,
@@ -582,7 +582,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [FWB]>], InstrStage<1, [FWB]>],
[10, 4, 4], [10, 4, 4],
[FPR_Bypass, FPR_Bypass, FPR_Bypass]>, [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
InstrItinData<FPAddSub , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_FPAddSub, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [FRACC]>, InstrStage<1, [FRACC]>,
@@ -595,7 +595,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [FWB]>], InstrStage<1, [FWB]>],
[10, 4, 4], [10, 4, 4],
[FPR_Bypass, FPR_Bypass, FPR_Bypass]>, [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
InstrItinData<FPCompare , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_FPCompare, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [FRACC]>, InstrStage<1, [FRACC]>,
@@ -608,7 +608,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [FWB]>], InstrStage<1, [FWB]>],
[10, 4, 4], [10, 4, 4],
[FPR_Bypass, FPR_Bypass, FPR_Bypass]>, [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
InstrItinData<FPDivD , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_FPDivD, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [FRACC]>, InstrStage<1, [FRACC]>,
@@ -621,7 +621,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<25, [FWB]>], InstrStage<25, [FWB]>],
[35, 4, 4], [35, 4, 4],
[NoBypass, FPR_Bypass, FPR_Bypass]>, [NoBypass, FPR_Bypass, FPR_Bypass]>,
InstrItinData<FPDivS , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_FPDivS, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [FRACC]>, InstrStage<1, [FRACC]>,
@@ -634,7 +634,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<13, [FWB]>], InstrStage<13, [FWB]>],
[23, 4, 4], [23, 4, 4],
[NoBypass, FPR_Bypass, FPR_Bypass]>, [NoBypass, FPR_Bypass, FPR_Bypass]>,
InstrItinData<FPFused , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_FPFused, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [FRACC]>, InstrStage<1, [FRACC]>,
@@ -647,7 +647,7 @@ def PPC440Itineraries : ProcessorItineraries<
InstrStage<1, [FWB]>], InstrStage<1, [FWB]>],
[10, 4, 4, 4], [10, 4, 4, 4],
[FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>, [FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
InstrItinData<FPRes , [InstrStage<1, [IFTH1, IFTH2]>, InstrItinData<IIC_FPRes, [InstrStage<1, [IFTH1, IFTH2]>,
InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [PDCD1, PDCD2]>,
InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [DISS1, DISS2]>,
InstrStage<1, [FRACC]>, InstrStage<1, [FRACC]>,

112
lib/Target/PowerPC/PPCScheduleA2.td
View File

@@ -25,117 +25,117 @@ def FU : FuncUnit; // FI pipeline
def PPCA2Itineraries : ProcessorItineraries< def PPCA2Itineraries : ProcessorItineraries<
[XU, FU], [], [ [XU, FU], [], [
InstrItinData<IntSimple , [InstrStage<1, [XU]>], InstrItinData<IIC_IntSimple, [InstrStage<1, [XU]>],
[1, 1, 1]>, [1, 1, 1]>,
InstrItinData<IntGeneral , [InstrStage<1, [XU]>], InstrItinData<IIC_IntGeneral, [InstrStage<1, [XU]>],
[2, 1, 1]>, [2, 1, 1]>,
InstrItinData<IntCompare , [InstrStage<1, [XU]>], InstrItinData<IIC_IntCompare, [InstrStage<1, [XU]>],
[2, 1, 1]>, [2, 1, 1]>,
InstrItinData<IntDivW , [InstrStage<1, [XU]>], InstrItinData<IIC_IntDivW, [InstrStage<1, [XU]>],
[39, 1, 1]>, [39, 1, 1]>,
InstrItinData<IntDivD , [InstrStage<1, [XU]>], InstrItinData<IIC_IntDivD, [InstrStage<1, [XU]>],
[71, 1, 1]>, [71, 1, 1]>,
InstrItinData<IntMulHW , [InstrStage<1, [XU]>], InstrItinData<IIC_IntMulHW, [InstrStage<1, [XU]>],
[5, 1, 1]>, [5, 1, 1]>,
InstrItinData<IntMulHWU , [InstrStage<1, [XU]>], InstrItinData<IIC_IntMulHWU, [InstrStage<1, [XU]>],
[5, 1, 1]>, [5, 1, 1]>,
InstrItinData<IntMulLI , [InstrStage<1, [XU]>], InstrItinData<IIC_IntMulLI, [InstrStage<1, [XU]>],
[6, 1, 1]>, [6, 1, 1]>,
InstrItinData<IntRotate , [InstrStage<1, [XU]>], InstrItinData<IIC_IntRotate, [InstrStage<1, [XU]>],
[2, 1, 1]>, [2, 1, 1]>,
InstrItinData<IntRotateD , [InstrStage<1, [XU]>], InstrItinData<IIC_IntRotateD, [InstrStage<1, [XU]>],
[2, 1, 1]>, [2, 1, 1]>,
InstrItinData<IntRotateDI , [InstrStage<1, [XU]>], InstrItinData<IIC_IntRotateDI, [InstrStage<1, [XU]>],
[2, 1, 1]>, [2, 1, 1]>,
InstrItinData<IntShift , [InstrStage<1, [XU]>], InstrItinData<IIC_IntShift, [InstrStage<1, [XU]>],
[2, 1, 1]>, [2, 1, 1]>,
InstrItinData<IntTrapW , [InstrStage<1, [XU]>], InstrItinData<IIC_IntTrapW, [InstrStage<1, [XU]>],
[2, 1]>, [2, 1]>,
InstrItinData<IntTrapD , [InstrStage<1, [XU]>], InstrItinData<IIC_IntTrapD, [InstrStage<1, [XU]>],
[2, 1]>, [2, 1]>,
InstrItinData<BrB , [InstrStage<1, [XU]>], InstrItinData<IIC_BrB, [InstrStage<1, [XU]>],
[6, 1, 1]>, [6, 1, 1]>,
InstrItinData<BrCR , [InstrStage<1, [XU]>], InstrItinData<IIC_BrCR, [InstrStage<1, [XU]>],
[1, 1, 1]>, [1, 1, 1]>,
InstrItinData<BrMCR , [InstrStage<1, [XU]>], InstrItinData<IIC_BrMCR, [InstrStage<1, [XU]>],
[5, 1, 1]>, [5, 1, 1]>,
InstrItinData<BrMCRX , [InstrStage<1, [XU]>], InstrItinData<IIC_BrMCRX, [InstrStage<1, [XU]>],
[1, 1, 1]>, [1, 1, 1]>,
InstrItinData<LdStDCBA , [InstrStage<1, [XU]>], InstrItinData<IIC_LdStDCBA, [InstrStage<1, [XU]>],
[1, 1, 1]>, [1, 1, 1]>,
InstrItinData<LdStDCBF , [InstrStage<1, [XU]>], InstrItinData<IIC_LdStDCBF, [InstrStage<1, [XU]>],
[1, 1, 1]>, [1, 1, 1]>,
InstrItinData<LdStDCBI , [InstrStage<1, [XU]>], InstrItinData<IIC_LdStDCBI, [InstrStage<1, [XU]>],
[1, 1, 1]>, [1, 1, 1]>,
InstrItinData<LdStLoad , [InstrStage<1, [XU]>], InstrItinData<IIC_LdStLoad, [InstrStage<1, [XU]>],
[6, 1, 1]>, [6, 1, 1]>,
InstrItinData<LdStLoadUpd , [InstrStage<1, [XU]>], InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [XU]>],
[6, 8, 1, 1]>, [6, 8, 1, 1]>,
InstrItinData<LdStLDU , [InstrStage<1, [XU]>], InstrItinData<IIC_LdStLDU, [InstrStage<1, [XU]>],
[6, 1, 1]>, [6, 1, 1]>,
InstrItinData<LdStStore , [InstrStage<1, [XU]>], InstrItinData<IIC_LdStStore, [InstrStage<1, [XU]>],
[1, 1, 1]>, [1, 1, 1]>,
InstrItinData<LdStStoreUpd, [InstrStage<1, [XU]>], InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [XU]>],
[2, 1, 1, 1]>, [2, 1, 1, 1]>,
InstrItinData<LdStICBI, [InstrStage<1, [XU]>], InstrItinData<IIC_LdStICBI, [InstrStage<1, [XU]>],
[16, 1, 1]>, [16, 1, 1]>,
InstrItinData<LdStSTFD , [InstrStage<1, [XU]>], InstrItinData<IIC_LdStSTFD, [InstrStage<1, [XU]>],
[1, 1, 1]>, [1, 1, 1]>,
InstrItinData<LdStSTFDU , [InstrStage<1, [XU]>], InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [XU]>],
[2, 1, 1, 1]>, [2, 1, 1, 1]>,
InstrItinData<LdStLFD , [InstrStage<1, [XU]>], InstrItinData<IIC_LdStLFD, [InstrStage<1, [XU]>],
[7, 1, 1]>, [7, 1, 1]>,
InstrItinData<LdStLFDU , [InstrStage<1, [XU]>], InstrItinData<IIC_LdStLFDU, [InstrStage<1, [XU]>],
[7, 9, 1, 1]>, [7, 9, 1, 1]>,
InstrItinData<LdStLHA , [InstrStage<1, [XU]>], InstrItinData<IIC_LdStLHA, [InstrStage<1, [XU]>],
[6, 1, 1]>, [6, 1, 1]>,
InstrItinData<LdStLHAU , [InstrStage<1, [XU]>], InstrItinData<IIC_LdStLHAU, [InstrStage<1, [XU]>],
[6, 8, 1, 1]>, [6, 8, 1, 1]>,
InstrItinData<LdStLWARX , [InstrStage<1, [XU]>], InstrItinData<IIC_LdStLWARX, [InstrStage<1, [XU]>],
[82, 1, 1]>, // L2 latency [82, 1, 1]>, // L2 latency
InstrItinData<LdStSTD , [InstrStage<1, [XU]>], InstrItinData<IIC_LdStSTD, [InstrStage<1, [XU]>],
[1, 1, 1]>, [1, 1, 1]>,
InstrItinData<LdStSTDU , [InstrStage<1, [XU]>], InstrItinData<IIC_LdStSTDU, [InstrStage<1, [XU]>],
[2, 1, 1, 1]>, [2, 1, 1, 1]>,
InstrItinData<LdStSTDCX , [InstrStage<1, [XU]>], InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [XU]>],
[82, 1, 1]>, // L2 latency [82, 1, 1]>, // L2 latency
InstrItinData<LdStSTWCX , [InstrStage<1, [XU]>], InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [XU]>],
[82, 1, 1]>, // L2 latency [82, 1, 1]>, // L2 latency
InstrItinData<LdStSync , [InstrStage<1, [XU]>], InstrItinData<IIC_LdStSync, [InstrStage<1, [XU]>],
[6]>, [6]>,
InstrItinData<SprISYNC , [InstrStage<1, [XU]>], InstrItinData<IIC_SprISYNC, [InstrStage<1, [XU]>],
[16]>, [16]>,
InstrItinData<SprMTMSR , [InstrStage<1, [XU]>], InstrItinData<IIC_SprMTMSR, [InstrStage<1, [XU]>],
[16, 1]>, [16, 1]>,
InstrItinData<SprMFCR , [InstrStage<1, [XU]>], InstrItinData<IIC_SprMFCR, [InstrStage<1, [XU]>],
[6, 1]>, [6, 1]>,
InstrItinData<SprMFMSR , [InstrStage<1, [XU]>], InstrItinData<IIC_SprMFMSR, [InstrStage<1, [XU]>],
[4, 1]>, [4, 1]>,
InstrItinData<SprMFSPR , [InstrStage<1, [XU]>], InstrItinData<IIC_SprMFSPR, [InstrStage<1, [XU]>],
[6, 1]>, [6, 1]>,
InstrItinData<SprMFTB , [InstrStage<1, [XU]>], InstrItinData<IIC_SprMFTB, [InstrStage<1, [XU]>],
[4, 1]>, [4, 1]>,
InstrItinData<SprMTSPR , [InstrStage<1, [XU]>], InstrItinData<IIC_SprMTSPR, [InstrStage<1, [XU]>],
[6, 1]>, [6, 1]>,
InstrItinData<SprRFI , [InstrStage<1, [XU]>], InstrItinData<IIC_SprRFI, [InstrStage<1, [XU]>],
[16]>, [16]>,
InstrItinData<SprSC , [InstrStage<1, [XU]>], InstrItinData<IIC_SprSC, [InstrStage<1, [XU]>],
[16]>, [16]>,
InstrItinData<FPGeneral , [InstrStage<1, [FU]>], InstrItinData<IIC_FPGeneral, [InstrStage<1, [FU]>],
[6, 1, 1]>, [6, 1, 1]>,
InstrItinData<FPAddSub , [InstrStage<1, [FU]>], InstrItinData<IIC_FPAddSub, [InstrStage<1, [FU]>],
[6, 1, 1]>, [6, 1, 1]>,
InstrItinData<FPCompare , [InstrStage<1, [FU]>], InstrItinData<IIC_FPCompare, [InstrStage<1, [FU]>],
[5, 1, 1]>, [5, 1, 1]>,
InstrItinData<FPDivD , [InstrStage<1, [FU]>], InstrItinData<IIC_FPDivD, [InstrStage<1, [FU]>],
[72, 1, 1]>, [72, 1, 1]>,
InstrItinData<FPDivS , [InstrStage<1, [FU]>], InstrItinData<IIC_FPDivS, [InstrStage<1, [FU]>],
[59, 1, 1]>, [59, 1, 1]>,
InstrItinData<FPSqrt , [InstrStage<1, [FU]>], InstrItinData<IIC_FPSqrt, [InstrStage<1, [FU]>],
[69, 1, 1]>, [69, 1, 1]>,
InstrItinData<FPFused , [InstrStage<1, [FU]>], InstrItinData<IIC_FPFused, [InstrStage<1, [FU]>],
[6, 1, 1, 1]>, [6, 1, 1, 1]>,
InstrItinData<FPRes , [InstrStage<1, [FU]>], InstrItinData<IIC_FPRes, [InstrStage<1, [FU]>],
[6, 1]> [6, 1]>
]>; ]>;

102
lib/Target/PowerPC/PPCScheduleE500mc.td
View File

@@ -41,213 +41,213 @@ def CR_Bypass : Bypass;
def PPCE500mcItineraries : ProcessorItineraries< def PPCE500mcItineraries : ProcessorItineraries<
[DIS0, DIS1, SFX0, SFX1, BU, CFX_DivBypass, CFX_0, LSU_0, FPU_0], [DIS0, DIS1, SFX0, SFX1, BU, CFX_DivBypass, CFX_0, LSU_0, FPU_0],
[CR_Bypass, GPR_Bypass, FPR_Bypass], [ [CR_Bypass, GPR_Bypass, FPR_Bypass], [
InstrItinData<IntSimple , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_IntSimple, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1]>], InstrStage<1, [SFX0, SFX1]>],
[4, 1, 1], // Latency = 1 [4, 1, 1], // Latency = 1
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntGeneral , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_IntGeneral, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1]>], InstrStage<1, [SFX0, SFX1]>],
[4, 1, 1], // Latency = 1 [4, 1, 1], // Latency = 1
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntCompare , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_IntCompare, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1]>], InstrStage<1, [SFX0, SFX1]>],
[5, 1, 1], // Latency = 1 or 2 [5, 1, 1], // Latency = 1 or 2
[CR_Bypass, GPR_Bypass, GPR_Bypass]>, [CR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntDivW , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_IntDivW, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [CFX_0], 0>, InstrStage<1, [CFX_0], 0>,
InstrStage<14, [CFX_DivBypass]>], InstrStage<14, [CFX_DivBypass]>],
[17, 1, 1], // Latency=4..35, Repeat= 4..35 [17, 1, 1], // Latency=4..35, Repeat= 4..35
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntMFFS , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_IntMFFS, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<8, [FPU_0]>], InstrStage<8, [FPU_0]>],
[11], // Latency = 8 [11], // Latency = 8
[FPR_Bypass]>, [FPR_Bypass]>,
InstrItinData<IntMTFSB0 , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<8, [FPU_0]>], InstrStage<8, [FPU_0]>],
[11, 1, 1], // Latency = 8 [11, 1, 1], // Latency = 8
[NoBypass, NoBypass, NoBypass]>, [NoBypass, NoBypass, NoBypass]>,
InstrItinData<IntMulHW , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_IntMulHW, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [CFX_0]>], InstrStage<1, [CFX_0]>],
[7, 1, 1], // Latency = 4, Repeat rate = 1 [7, 1, 1], // Latency = 4, Repeat rate = 1
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntMulHWU , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_IntMulHWU, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [CFX_0]>], InstrStage<1, [CFX_0]>],
[7, 1, 1], // Latency = 4, Repeat rate = 1 [7, 1, 1], // Latency = 4, Repeat rate = 1
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntMulLI , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_IntMulLI, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [CFX_0]>], InstrStage<1, [CFX_0]>],
[7, 1, 1], // Latency = 4, Repeat rate = 1 [7, 1, 1], // Latency = 4, Repeat rate = 1
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntRotate , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_IntRotate, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1]>], InstrStage<1, [SFX0, SFX1]>],
[4, 1, 1], // Latency = 1 [4, 1, 1], // Latency = 1
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntShift , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_IntShift, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1]>], InstrStage<1, [SFX0, SFX1]>],
[4, 1, 1], // Latency = 1 [4, 1, 1], // Latency = 1
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntTrapW , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_IntTrapW, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<2, [SFX0]>], InstrStage<2, [SFX0]>],
[5, 1], // Latency = 2, Repeat rate = 2 [5, 1], // Latency = 2, Repeat rate = 2
[GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass]>,
InstrItinData<BrB , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_BrB, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [BU]>], InstrStage<1, [BU]>],
[4, 1], // Latency = 1 [4, 1], // Latency = 1
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<BrCR , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_BrCR, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [BU]>], InstrStage<1, [BU]>],
[4, 1, 1], // Latency = 1 [4, 1, 1], // Latency = 1
[CR_Bypass, CR_Bypass, CR_Bypass]>, [CR_Bypass, CR_Bypass, CR_Bypass]>,
InstrItinData<BrMCR , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_BrMCR, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [BU]>], InstrStage<1, [BU]>],
[4, 1], // Latency = 1 [4, 1], // Latency = 1
[CR_Bypass, CR_Bypass]>, [CR_Bypass, CR_Bypass]>,
InstrItinData<BrMCRX , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_BrMCRX, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1]>], InstrStage<1, [SFX0, SFX1]>],
[4, 1, 1], // Latency = 1 [4, 1, 1], // Latency = 1
[CR_Bypass, GPR_Bypass]>, [CR_Bypass, GPR_Bypass]>,
InstrItinData<LdStDCBA , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStDCBA, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[6, 1], // Latency = 3, Repeat rate = 1 [6, 1], // Latency = 3, Repeat rate = 1
[GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass]>,
InstrItinData<LdStDCBF , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStDCBF, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass]>,
InstrItinData<LdStDCBI , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStDCBI, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass]>,
InstrItinData<LdStLoad , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStLoad, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass]>,
InstrItinData<LdStLoadUpd , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1], 0>, InstrStage<1, [SFX0, SFX1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[GPR_Bypass, GPR_Bypass], [GPR_Bypass, GPR_Bypass],
2>, // 2 micro-ops 2>, // 2 micro-ops
InstrItinData<LdStStore , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStStore, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<LdStStoreUpd, [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1], 0>, InstrStage<1, [SFX0, SFX1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[NoBypass, GPR_Bypass], [NoBypass, GPR_Bypass],
2>, // 2 micro-ops 2>, // 2 micro-ops
InstrItinData<LdStICBI , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStICBI, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<LdStSTFD , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStSTFD, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[6, 1, 1], // Latency = 3 [6, 1, 1], // Latency = 3
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<LdStSTFDU , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1], 0>, InstrStage<1, [SFX0, SFX1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[6, 1, 1], // Latency = 3 [6, 1, 1], // Latency = 3
[GPR_Bypass, GPR_Bypass, GPR_Bypass], [GPR_Bypass, GPR_Bypass, GPR_Bypass],
2>, // 2 micro-ops 2>, // 2 micro-ops
InstrItinData<LdStLFD , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStLFD, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[7, 1, 1], // Latency = 4 [7, 1, 1], // Latency = 4
[FPR_Bypass, GPR_Bypass, GPR_Bypass]>, [FPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<LdStLFDU , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStLFDU, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1], 0>, InstrStage<1, [SFX0, SFX1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[7, 1, 1], // Latency = 4 [7, 1, 1], // Latency = 4
[FPR_Bypass, GPR_Bypass, GPR_Bypass], [FPR_Bypass, GPR_Bypass, GPR_Bypass],
2>, // 2 micro-ops 2>, // 2 micro-ops
InstrItinData<LdStLHA , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStLHA, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass]>,
InstrItinData<LdStLHAU , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStLHAU, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1], 0>, InstrStage<1, [SFX0, SFX1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass]>,
InstrItinData<LdStLMW , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStLMW, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[7, 1], // Latency = r+3 [7, 1], // Latency = r+3
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<LdStLWARX , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStLWARX, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<3, [LSU_0]>], InstrStage<3, [LSU_0]>],
[6, 1, 1], // Latency = 3, Repeat rate = 3 [6, 1, 1], // Latency = 3, Repeat rate = 3
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<LdStSTWCX , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[6, 1], // Latency = 3 [6, 1], // Latency = 3
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<LdStSync , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStSync, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>]>, InstrStage<1, [LSU_0]>]>,
InstrItinData<SprMFSR , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_SprMFSR, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<4, [SFX0]>], InstrStage<4, [SFX0]>],
[7, 1], [7, 1],
[GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass]>,
InstrItinData<SprMTMSR , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_SprMTMSR, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<2, [SFX0, SFX1]>], InstrStage<2, [SFX0, SFX1]>],
[5, 1], // Latency = 2, Repeat rate = 4 [5, 1], // Latency = 2, Repeat rate = 4
[GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass]>,
InstrItinData<SprMTSR , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_SprMTSR, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0]>], InstrStage<1, [SFX0]>],
[5, 1], [5, 1],
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<SprTLBSYNC , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0], 0>]>, InstrStage<1, [LSU_0], 0>]>,
InstrItinData<SprMFCR , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_SprMFCR, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<5, [SFX0]>], InstrStage<5, [SFX0]>],
[8, 1], [8, 1],
[GPR_Bypass, CR_Bypass]>, [GPR_Bypass, CR_Bypass]>,
InstrItinData<SprMFMSR , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_SprMFMSR, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<4, [SFX0]>], InstrStage<4, [SFX0]>],
[7, 1], // Latency = 4, Repeat rate = 4 [7, 1], // Latency = 4, Repeat rate = 4
[GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass]>,
InstrItinData<SprMFSPR , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_SprMFSPR, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1]>], InstrStage<1, [SFX0, SFX1]>],
[4, 1], // Latency = 1, Repeat rate = 1 [4, 1], // Latency = 1, Repeat rate = 1
[GPR_Bypass, CR_Bypass]>, [GPR_Bypass, CR_Bypass]>,
InstrItinData<SprMFTB , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_SprMFTB, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<4, [SFX0]>], InstrStage<4, [SFX0]>],
[7, 1], // Latency = 4, Repeat rate = 4 [7, 1], // Latency = 4, Repeat rate = 4
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<SprMTSPR , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_SprMTSPR, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1]>], InstrStage<1, [SFX0, SFX1]>],
[4, 1], // Latency = 1, Repeat rate = 1 [4, 1], // Latency = 1, Repeat rate = 1
[CR_Bypass, GPR_Bypass]>, [CR_Bypass, GPR_Bypass]>,
InstrItinData<SprMTSRIN , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_SprMTSRIN, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0]>], InstrStage<1, [SFX0]>],
[4, 1], [4, 1],
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<FPGeneral , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_FPGeneral, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<2, [FPU_0]>], InstrStage<2, [FPU_0]>],
[11, 1, 1], // Latency = 8, Repeat rate = 2 [11, 1, 1], // Latency = 8, Repeat rate = 2
[FPR_Bypass, FPR_Bypass, FPR_Bypass]>, [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
InstrItinData<FPAddSub , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_FPAddSub, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<4, [FPU_0]>], InstrStage<4, [FPU_0]>],
[13, 1, 1], // Latency = 10, Repeat rate = 4 [13, 1, 1], // Latency = 10, Repeat rate = 4
[FPR_Bypass, FPR_Bypass, FPR_Bypass]>, [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
InstrItinData<FPCompare , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_FPCompare, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<2, [FPU_0]>], InstrStage<2, [FPU_0]>],
[11, 1, 1], // Latency = 8, Repeat rate = 2 [11, 1, 1], // Latency = 8, Repeat rate = 2
[CR_Bypass, FPR_Bypass, FPR_Bypass]>, [CR_Bypass, FPR_Bypass, FPR_Bypass]>,
InstrItinData<FPDivD , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_FPDivD, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<68, [FPU_0]>], InstrStage<68, [FPU_0]>],
[71, 1, 1], // Latency = 68, Repeat rate = 68 [71, 1, 1], // Latency = 68, Repeat rate = 68
[FPR_Bypass, FPR_Bypass, FPR_Bypass]>, [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
InstrItinData<FPDivS , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_FPDivS, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<38, [FPU_0]>], InstrStage<38, [FPU_0]>],
[41, 1, 1], // Latency = 38, Repeat rate = 38 [41, 1, 1], // Latency = 38, Repeat rate = 38
[FPR_Bypass, FPR_Bypass, FPR_Bypass]>, [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
InstrItinData<FPFused , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_FPFused, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<4, [FPU_0]>], InstrStage<4, [FPU_0]>],
[13, 1, 1, 1], // Latency = 10, Repeat rate = 4 [13, 1, 1, 1], // Latency = 10, Repeat rate = 4
[FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>, [FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
InstrItinData<FPRes , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_FPRes, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<38, [FPU_0]>], InstrStage<38, [FPU_0]>],
[41, 1], // Latency = 38, Repeat rate = 38 [41, 1], // Latency = 38, Repeat rate = 38
[FPR_Bypass, FPR_Bypass]> [FPR_Bypass, FPR_Bypass]>

116
lib/Target/PowerPC/PPCScheduleE5500.td
View File

@@ -45,252 +45,252 @@ def PPCE5500Itineraries : ProcessorItineraries<
[DIS0, DIS1, SFX0, SFX1, BU, CFX_DivBypass, CFX_0, CFX_1, [DIS0, DIS1, SFX0, SFX1, BU, CFX_DivBypass, CFX_0, CFX_1,
LSU_0, FPU_0], LSU_0, FPU_0],
[CR_Bypass, GPR_Bypass, FPR_Bypass], [ [CR_Bypass, GPR_Bypass, FPR_Bypass], [
InstrItinData<IntSimple , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_IntSimple, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1]>], InstrStage<1, [SFX0, SFX1]>],
[5, 2, 2], // Latency = 1 [5, 2, 2], // Latency = 1
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntGeneral , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_IntGeneral, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1]>], InstrStage<1, [SFX0, SFX1]>],
[5, 2, 2], // Latency = 1 [5, 2, 2], // Latency = 1
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntCompare , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_IntCompare, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1]>], InstrStage<1, [SFX0, SFX1]>],
[6, 2, 2], // Latency = 1 or 2 [6, 2, 2], // Latency = 1 or 2
[CR_Bypass, GPR_Bypass, GPR_Bypass]>, [CR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntDivD , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_IntDivD, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [CFX_0], 0>, InstrStage<1, [CFX_0], 0>,
InstrStage<26, [CFX_DivBypass]>], InstrStage<26, [CFX_DivBypass]>],
[30, 2, 2], // Latency= 4..26, Repeat rate= 4..26 [30, 2, 2], // Latency= 4..26, Repeat rate= 4..26
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntDivW , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_IntDivW, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [CFX_0], 0>, InstrStage<1, [CFX_0], 0>,
InstrStage<16, [CFX_DivBypass]>], InstrStage<16, [CFX_DivBypass]>],
[20, 2, 2], // Latency= 4..16, Repeat rate= 4..16 [20, 2, 2], // Latency= 4..16, Repeat rate= 4..16
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntMFFS , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_IntMFFS, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [FPU_0]>], InstrStage<1, [FPU_0]>],
[11], // Latency = 7, Repeat rate = 1 [11], // Latency = 7, Repeat rate = 1
[FPR_Bypass]>, [FPR_Bypass]>,
InstrItinData<IntMTFSB0 , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_IntMTFSB0, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<7, [FPU_0]>], InstrStage<7, [FPU_0]>],
[11, 2, 2], // Latency = 7, Repeat rate = 7 [11, 2, 2], // Latency = 7, Repeat rate = 7
[NoBypass, NoBypass, NoBypass]>, [NoBypass, NoBypass, NoBypass]>,
InstrItinData<IntMulHD , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_IntMulHD, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [CFX_0], 0>, InstrStage<1, [CFX_0], 0>,
InstrStage<2, [CFX_1]>], InstrStage<2, [CFX_1]>],
[9, 2, 2], // Latency = 4..7, Repeat rate = 2..4 [9, 2, 2], // Latency = 4..7, Repeat rate = 2..4
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntMulHW , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_IntMulHW, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [CFX_0], 0>, InstrStage<1, [CFX_0], 0>,
InstrStage<1, [CFX_1]>], InstrStage<1, [CFX_1]>],
[8, 2, 2], // Latency = 4, Repeat rate = 1 [8, 2, 2], // Latency = 4, Repeat rate = 1
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntMulHWU , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_IntMulHWU, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [CFX_0], 0>, InstrStage<1, [CFX_0], 0>,
InstrStage<1, [CFX_1]>], InstrStage<1, [CFX_1]>],
[8, 2, 2], // Latency = 4, Repeat rate = 1 [8, 2, 2], // Latency = 4, Repeat rate = 1
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntMulLI , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_IntMulLI, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [CFX_0], 0>, InstrStage<1, [CFX_0], 0>,
InstrStage<2, [CFX_1]>], InstrStage<2, [CFX_1]>],
[8, 2, 2], // Latency = 4 or 5, Repeat = 2 [8, 2, 2], // Latency = 4 or 5, Repeat = 2
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntRotate , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_IntRotate, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1]>], InstrStage<1, [SFX0, SFX1]>],
[5, 2, 2], // Latency = 1 [5, 2, 2], // Latency = 1
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntRotateD , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_IntRotateD, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<2, [SFX0, SFX1]>], InstrStage<2, [SFX0, SFX1]>],
[6, 2, 2], // Latency = 2, Repeat rate = 2 [6, 2, 2], // Latency = 2, Repeat rate = 2
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntRotateDI , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_IntRotateDI, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1]>], InstrStage<1, [SFX0, SFX1]>],
[5, 2, 2], // Latency = 1, Repeat rate = 1 [5, 2, 2], // Latency = 1, Repeat rate = 1
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntShift , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_IntShift, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<2, [SFX0, SFX1]>], InstrStage<2, [SFX0, SFX1]>],
[6, 2, 2], // Latency = 2, Repeat rate = 2 [6, 2, 2], // Latency = 2, Repeat rate = 2
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<IntTrapW , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_IntTrapW, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<2, [SFX0]>], InstrStage<2, [SFX0]>],
[6, 2], // Latency = 2, Repeat rate = 2 [6, 2], // Latency = 2, Repeat rate = 2
[GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass]>,
InstrItinData<BrB , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_BrB, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [BU]>], InstrStage<1, [BU]>],
[5, 2], // Latency = 1 [5, 2], // Latency = 1
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<BrCR , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_BrCR, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [BU]>], InstrStage<1, [BU]>],
[5, 2, 2], // Latency = 1 [5, 2, 2], // Latency = 1
[CR_Bypass, CR_Bypass, CR_Bypass]>, [CR_Bypass, CR_Bypass, CR_Bypass]>,
InstrItinData<BrMCR , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_BrMCR, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [BU]>], InstrStage<1, [BU]>],
[5, 2], // Latency = 1 [5, 2], // Latency = 1
[CR_Bypass, CR_Bypass]>, [CR_Bypass, CR_Bypass]>,
InstrItinData<BrMCRX , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_BrMCRX, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [CFX_0]>], InstrStage<1, [CFX_0]>],
[5, 2, 2], // Latency = 1 [5, 2, 2], // Latency = 1
[CR_Bypass, GPR_Bypass]>, [CR_Bypass, GPR_Bypass]>,
InstrItinData<LdStDCBA , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStDCBA, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[7, 2], // Latency = 3, Repeat rate = 1 [7, 2], // Latency = 3, Repeat rate = 1
[GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass]>,
InstrItinData<LdStDCBF , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStDCBF, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[7, 2], // Latency = 3, Repeat rate = 1 [7, 2], // Latency = 3, Repeat rate = 1
[GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass]>,
InstrItinData<LdStDCBI , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStDCBI, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[7, 2], // Latency = 3, Repeat rate = 1 [7, 2], // Latency = 3, Repeat rate = 1
[GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass]>,
InstrItinData<LdStLoad , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStLoad, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[7, 2], // Latency = 3 [7, 2], // Latency = 3
[GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass]>,
InstrItinData<LdStLoadUpd , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStLoadUpd, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1], 0>, InstrStage<1, [SFX0, SFX1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[7, 2], // Latency = 3, Repeat rate = 1 [7, 2], // Latency = 3, Repeat rate = 1
[GPR_Bypass, GPR_Bypass], [GPR_Bypass, GPR_Bypass],
2>, // 2 micro-ops 2>, // 2 micro-ops
InstrItinData<LdStLD , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStLD, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[7, 2], // Latency = 3, Repeat rate = 1 [7, 2], // Latency = 3, Repeat rate = 1
[GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass]>,
InstrItinData<LdStLDARX , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStLDARX, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<3, [LSU_0]>], InstrStage<3, [LSU_0]>],
[7, 2], // Latency = 3, Repeat rate = 3 [7, 2], // Latency = 3, Repeat rate = 3
[GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass]>,
InstrItinData<LdStLDU , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStLDU, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1], 0>, InstrStage<1, [SFX0, SFX1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[7, 2], // Latency = 3, Repeat rate = 1 [7, 2], // Latency = 3, Repeat rate = 1
[GPR_Bypass, GPR_Bypass], [GPR_Bypass, GPR_Bypass],
2>, // 2 micro-ops 2>, // 2 micro-ops
InstrItinData<LdStStore , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStStore, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[7, 2], // Latency = 3, Repeat rate = 1 [7, 2], // Latency = 3, Repeat rate = 1
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<LdStStoreUpd, [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1], 0>, InstrStage<1, [SFX0, SFX1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[7, 2], // Latency = 3, Repeat rate = 1 [7, 2], // Latency = 3, Repeat rate = 1
[NoBypass, GPR_Bypass], [NoBypass, GPR_Bypass],
2>, // 2 micro-ops 2>, // 2 micro-ops
InstrItinData<LdStICBI , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStICBI, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[7, 2], // Latency = 3, Repeat rate = 1 [7, 2], // Latency = 3, Repeat rate = 1
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<LdStSTFD , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStSTFD, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[7, 2, 2], // Latency = 3, Repeat rate = 1 [7, 2, 2], // Latency = 3, Repeat rate = 1
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<LdStSTFDU , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStSTFDU, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1], 0>, InstrStage<1, [SFX0, SFX1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[7, 2, 2], // Latency = 3, Repeat rate = 1 [7, 2, 2], // Latency = 3, Repeat rate = 1
[GPR_Bypass, GPR_Bypass, GPR_Bypass], [GPR_Bypass, GPR_Bypass, GPR_Bypass],
2>, // 2 micro-ops 2>, // 2 micro-ops
InstrItinData<LdStLFD , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStLFD, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[8, 2, 2], // Latency = 4, Repeat rate = 1 [8, 2, 2], // Latency = 4, Repeat rate = 1
[FPR_Bypass, GPR_Bypass, GPR_Bypass], [FPR_Bypass, GPR_Bypass, GPR_Bypass],
2>, // 2 micro-ops 2>, // 2 micro-ops
InstrItinData<LdStLFDU , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStLFDU, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1], 0>, InstrStage<1, [SFX0, SFX1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[8, 2, 2], // Latency = 4, Repeat rate = 1 [8, 2, 2], // Latency = 4, Repeat rate = 1
[FPR_Bypass, GPR_Bypass, GPR_Bypass], [FPR_Bypass, GPR_Bypass, GPR_Bypass],
2>, // 2 micro-ops 2>, // 2 micro-ops
InstrItinData<LdStLHA , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStLHA, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[7, 2], // Latency = 3 [7, 2], // Latency = 3
[GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass]>,
InstrItinData<LdStLHAU , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStLHAU, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1], 0>, InstrStage<1, [SFX0, SFX1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[7, 2], // Latency = 3, Repeat rate = 1 [7, 2], // Latency = 3, Repeat rate = 1
[GPR_Bypass, GPR_Bypass], [GPR_Bypass, GPR_Bypass],
2>, // 2 micro-ops 2>, // 2 micro-ops
InstrItinData<LdStLMW , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStLMW, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<4, [LSU_0]>], InstrStage<4, [LSU_0]>],
[8, 2], // Latency = r+3, Repeat rate = r+3 [8, 2], // Latency = r+3, Repeat rate = r+3
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<LdStLWARX , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStLWARX, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<3, [LSU_0]>], InstrStage<3, [LSU_0]>],
[7, 2, 2], // Latency = 3, Repeat rate = 3 [7, 2, 2], // Latency = 3, Repeat rate = 3
[GPR_Bypass, GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass, GPR_Bypass]>,
InstrItinData<LdStSTD , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStSTD, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[7, 2], // Latency = 3, Repeat rate = 1 [7, 2], // Latency = 3, Repeat rate = 1
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<LdStSTDCX , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStSTDCX, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[7, 2], // Latency = 3, Repeat rate = 1 [7, 2], // Latency = 3, Repeat rate = 1
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<LdStSTDU , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStSTDU, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1], 0>, InstrStage<1, [SFX0, SFX1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[7, 2], // Latency = 3, Repeat rate = 1 [7, 2], // Latency = 3, Repeat rate = 1
[NoBypass, GPR_Bypass], [NoBypass, GPR_Bypass],
2>, // 2 micro-ops 2>, // 2 micro-ops
InstrItinData<LdStSTWCX , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStSTWCX, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>], InstrStage<1, [LSU_0]>],
[7, 2], // Latency = 3, Repeat rate = 1 [7, 2], // Latency = 3, Repeat rate = 1
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<LdStSync , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_LdStSync, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0]>]>, InstrStage<1, [LSU_0]>]>,
InstrItinData<SprMTMSR , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_SprMTMSR, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<2, [CFX_0]>], InstrStage<2, [CFX_0]>],
[6, 2], // Latency = 2, Repeat rate = 4 [6, 2], // Latency = 2, Repeat rate = 4
[GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass]>,
InstrItinData<SprTLBSYNC , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [LSU_0], 0>]>, InstrStage<1, [LSU_0], 0>]>,
InstrItinData<SprMFCR , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_SprMFCR, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<5, [CFX_0]>], InstrStage<5, [CFX_0]>],
[9, 2], // Latency = 5, Repeat rate = 5 [9, 2], // Latency = 5, Repeat rate = 5
[GPR_Bypass, CR_Bypass]>, [GPR_Bypass, CR_Bypass]>,
InstrItinData<SprMFMSR , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_SprMFMSR, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<4, [SFX0]>], InstrStage<4, [SFX0]>],
[8, 2], // Latency = 4, Repeat rate = 4 [8, 2], // Latency = 4, Repeat rate = 4
[GPR_Bypass, GPR_Bypass]>, [GPR_Bypass, GPR_Bypass]>,
InstrItinData<SprMFSPR , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_SprMFSPR, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [CFX_0]>], InstrStage<1, [CFX_0]>],
[5], // Latency = 1, Repeat rate = 1 [5], // Latency = 1, Repeat rate = 1
[GPR_Bypass]>, [GPR_Bypass]>,
InstrItinData<SprMFTB , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_SprMFTB, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<4, [CFX_0]>], InstrStage<4, [CFX_0]>],
[8, 2], // Latency = 4, Repeat rate = 4 [8, 2], // Latency = 4, Repeat rate = 4
[NoBypass, GPR_Bypass]>, [NoBypass, GPR_Bypass]>,
InstrItinData<SprMTSPR , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_SprMTSPR, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [SFX0, SFX1]>], InstrStage<1, [SFX0, SFX1]>],
[5], // Latency = 1, Repeat rate = 1 [5], // Latency = 1, Repeat rate = 1
[GPR_Bypass]>, [GPR_Bypass]>,
InstrItinData<FPGeneral , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_FPGeneral, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [FPU_0]>], InstrStage<1, [FPU_0]>],
[11, 2, 2], // Latency = 7, Repeat rate = 1 [11, 2, 2], // Latency = 7, Repeat rate = 1
[FPR_Bypass, FPR_Bypass, FPR_Bypass]>, [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
InstrItinData<FPAddSub , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_FPAddSub, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [FPU_0]>], InstrStage<1, [FPU_0]>],
[11, 2, 2], // Latency = 7, Repeat rate = 1 [11, 2, 2], // Latency = 7, Repeat rate = 1
[FPR_Bypass, FPR_Bypass, FPR_Bypass]>, [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
InstrItinData<FPCompare , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_FPCompare, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [FPU_0]>], InstrStage<1, [FPU_0]>],
[11, 2, 2], // Latency = 7, Repeat rate = 1 [11, 2, 2], // Latency = 7, Repeat rate = 1
[CR_Bypass, FPR_Bypass, FPR_Bypass]>, [CR_Bypass, FPR_Bypass, FPR_Bypass]>,
InstrItinData<FPDivD , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_FPDivD, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<31, [FPU_0]>], InstrStage<31, [FPU_0]>],
[39, 2, 2], // Latency = 35, Repeat rate = 31 [39, 2, 2], // Latency = 35, Repeat rate = 31
[FPR_Bypass, FPR_Bypass, FPR_Bypass]>, [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
InstrItinData<FPDivS , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_FPDivS, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<16, [FPU_0]>], InstrStage<16, [FPU_0]>],
[24, 2, 2], // Latency = 20, Repeat rate = 16 [24, 2, 2], // Latency = 20, Repeat rate = 16
[FPR_Bypass, FPR_Bypass, FPR_Bypass]>, [FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
InstrItinData<FPFused , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_FPFused, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<1, [FPU_0]>], InstrStage<1, [FPU_0]>],
[11, 2, 2, 2], // Latency = 7, Repeat rate = 1 [11, 2, 2, 2], // Latency = 7, Repeat rate = 1
[FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>, [FPR_Bypass, FPR_Bypass, FPR_Bypass, FPR_Bypass]>,
InstrItinData<FPRes , [InstrStage<1, [DIS0, DIS1], 0>, InstrItinData<IIC_FPRes, [InstrStage<1, [DIS0, DIS1], 0>,
InstrStage<2, [FPU_0]>], InstrStage<2, [FPU_0]>],
[12, 2], // Latency = 8, Repeat rate = 2 [12, 2], // Latency = 8, Repeat rate = 2
[FPR_Bypass, FPR_Bypass]> [FPR_Bypass, FPR_Bypass]>

108
lib/Target/PowerPC/PPCScheduleG3.td
View File

@@ -14,58 +14,58 @@
def G3Itineraries : ProcessorItineraries< def G3Itineraries : ProcessorItineraries<
[IU1, IU2, FPU1, BPU, SRU, SLU], [], [ [IU1, IU2, FPU1, BPU, SRU, SLU], [], [
InstrItinData<IntSimple , [InstrStage<1, [IU1, IU2]>]>, InstrItinData<IIC_IntSimple , [InstrStage<1, [IU1, IU2]>]>,
InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2]>]>, InstrItinData<IIC_IntGeneral , [InstrStage<1, [IU1, IU2]>]>,
InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2]>]>, InstrItinData<IIC_IntCompare , [InstrStage<1, [IU1, IU2]>]>,
InstrItinData<IntDivW , [InstrStage<19, [IU1]>]>, InstrItinData<IIC_IntDivW , [InstrStage<19, [IU1]>]>,
InstrItinData<IntMFFS , [InstrStage<1, [FPU1]>]>, InstrItinData<IIC_IntMFFS , [InstrStage<1, [FPU1]>]>,
InstrItinData<IntMTFSB0 , [InstrStage<3, [FPU1]>]>, InstrItinData<IIC_IntMTFSB0 , [InstrStage<3, [FPU1]>]>,
InstrItinData<IntMulHW , [InstrStage<5, [IU1]>]>, InstrItinData<IIC_IntMulHW , [InstrStage<5, [IU1]>]>,
InstrItinData<IntMulHWU , [InstrStage<6, [IU1]>]>, InstrItinData<IIC_IntMulHWU , [InstrStage<6, [IU1]>]>,
InstrItinData<IntMulLI , [InstrStage<3, [IU1]>]>, InstrItinData<IIC_IntMulLI , [InstrStage<3, [IU1]>]>,
InstrItinData<IntRotate , [InstrStage<1, [IU1, IU2]>]>, InstrItinData<IIC_IntRotate , [InstrStage<1, [IU1, IU2]>]>,
InstrItinData<IntShift , [InstrStage<1, [IU1, IU2]>]>, InstrItinData<IIC_IntShift , [InstrStage<1, [IU1, IU2]>]>,
InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2]>]>, InstrItinData<IIC_IntTrapW , [InstrStage<2, [IU1, IU2]>]>,
InstrItinData<BrB , [InstrStage<1, [BPU]>]>, InstrItinData<IIC_BrB , [InstrStage<1, [BPU]>]>,
InstrItinData<BrCR , [InstrStage<1, [SRU]>]>, InstrItinData<IIC_BrCR , [InstrStage<1, [SRU]>]>,
InstrItinData<BrMCR , [InstrStage<1, [SRU]>]>, InstrItinData<IIC_BrMCR , [InstrStage<1, [SRU]>]>,
InstrItinData<BrMCRX , [InstrStage<1, [SRU]>]>, InstrItinData<IIC_BrMCRX , [InstrStage<1, [SRU]>]>,
InstrItinData<LdStDCBA , [InstrStage<2, [SLU]>]>, InstrItinData<IIC_LdStDCBA , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStDCBF , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStDCBI , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStDCBI , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLoad , [InstrStage<2, [SLU]>]>, InstrItinData<IIC_LdStLoad , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLoadUpd , [InstrStage<2, [SLU]>]>, InstrItinData<IIC_LdStLoadUpd , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStStore , [InstrStage<2, [SLU]>]>, InstrItinData<IIC_LdStStore , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStStoreUpd, [InstrStage<2, [SLU]>]>, InstrItinData<IIC_LdStStoreUpd, [InstrStage<2, [SLU]>]>,
InstrItinData<LdStICBI , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStICBI , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStSTFD , [InstrStage<2, [SLU]>]>, InstrItinData<IIC_LdStSTFD , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStSTFDU , [InstrStage<2, [SLU]>]>, InstrItinData<IIC_LdStSTFDU , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLFD , [InstrStage<2, [SLU]>]>, InstrItinData<IIC_LdStLFD , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLFDU , [InstrStage<2, [SLU]>]>, InstrItinData<IIC_LdStLFDU , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLHA , [InstrStage<2, [SLU]>]>, InstrItinData<IIC_LdStLHA , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLHAU , [InstrStage<2, [SLU]>]>, InstrItinData<IIC_LdStLHAU , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLMW , [InstrStage<34, [SLU]>]>, InstrItinData<IIC_LdStLMW , [InstrStage<34, [SLU]>]>,
InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStLWARX , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStSTWCX , [InstrStage<8, [SLU]>]>, InstrItinData<IIC_LdStSTWCX , [InstrStage<8, [SLU]>]>,
InstrItinData<LdStSync , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStSync , [InstrStage<3, [SLU]>]>,
InstrItinData<SprISYNC , [InstrStage<2, [SRU]>]>, InstrItinData<IIC_SprISYNC , [InstrStage<2, [SRU]>]>,
InstrItinData<SprMFSR , [InstrStage<3, [SRU]>]>, InstrItinData<IIC_SprMFSR , [InstrStage<3, [SRU]>]>,
InstrItinData<SprMTMSR , [InstrStage<1, [SRU]>]>, InstrItinData<IIC_SprMTMSR , [InstrStage<1, [SRU]>]>,
InstrItinData<SprMTSR , [InstrStage<2, [SRU]>]>, InstrItinData<IIC_SprMTSR , [InstrStage<2, [SRU]>]>,
InstrItinData<SprTLBSYNC , [InstrStage<3, [SRU]>]>, InstrItinData<IIC_SprTLBSYNC , [InstrStage<3, [SRU]>]>,
InstrItinData<SprMFCR , [InstrStage<1, [SRU]>]>, InstrItinData<IIC_SprMFCR , [InstrStage<1, [SRU]>]>,
InstrItinData<SprMFMSR , [InstrStage<1, [SRU]>]>, InstrItinData<IIC_SprMFMSR , [InstrStage<1, [SRU]>]>,
InstrItinData<SprMFSPR , [InstrStage<3, [SRU]>]>, InstrItinData<IIC_SprMFSPR , [InstrStage<3, [SRU]>]>,
InstrItinData<SprMFTB , [InstrStage<3, [SRU]>]>, InstrItinData<IIC_SprMFTB , [InstrStage<3, [SRU]>]>,
InstrItinData<SprMTSPR , [InstrStage<2, [SRU]>]>, InstrItinData<IIC_SprMTSPR , [InstrStage<2, [SRU]>]>,
InstrItinData<SprMTSRIN , [InstrStage<2, [SRU]>]>, InstrItinData<IIC_SprMTSRIN , [InstrStage<2, [SRU]>]>,
InstrItinData<SprRFI , [InstrStage<2, [SRU]>]>, InstrItinData<IIC_SprRFI , [InstrStage<2, [SRU]>]>,
InstrItinData<SprSC , [InstrStage<2, [SRU]>]>, InstrItinData<IIC_SprSC , [InstrStage<2, [SRU]>]>,
InstrItinData<FPGeneral , [InstrStage<1, [FPU1]>]>, InstrItinData<IIC_FPGeneral , [InstrStage<1, [FPU1]>]>,
InstrItinData<FPAddSub , [InstrStage<1, [FPU1]>]>, InstrItinData<IIC_FPAddSub , [InstrStage<1, [FPU1]>]>,
InstrItinData<FPCompare , [InstrStage<1, [FPU1]>]>, InstrItinData<IIC_FPCompare , [InstrStage<1, [FPU1]>]>,
InstrItinData<FPDivD , [InstrStage<31, [FPU1]>]>, InstrItinData<IIC_FPDivD , [InstrStage<31, [FPU1]>]>,
InstrItinData<FPDivS , [InstrStage<17, [FPU1]>]>, InstrItinData<IIC_FPDivS , [InstrStage<17, [FPU1]>]>,
InstrItinData<FPFused , [InstrStage<2, [FPU1]>]>, InstrItinData<IIC_FPFused , [InstrStage<2, [FPU1]>]>,
InstrItinData<FPRes , [InstrStage<10, [FPU1]>]> InstrItinData<IIC_FPRes , [InstrStage<10, [FPU1]>]>
]>; ]>;

130
lib/Target/PowerPC/PPCScheduleG4.td
View File

@@ -13,69 +13,69 @@
def G4Itineraries : ProcessorItineraries< def G4Itineraries : ProcessorItineraries<
[IU1, IU2, SLU, SRU, BPU, FPU1, VIU1, VIU2, VPU, VFPU], [], [ [IU1, IU2, SLU, SRU, BPU, FPU1, VIU1, VIU2, VPU, VFPU], [], [
InstrItinData<IntSimple , [InstrStage<1, [IU1, IU2]>]>, InstrItinData<IIC_IntSimple , [InstrStage<1, [IU1, IU2]>]>,
InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2]>]>, InstrItinData<IIC_IntGeneral , [InstrStage<1, [IU1, IU2]>]>,
InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2]>]>, InstrItinData<IIC_IntCompare , [InstrStage<1, [IU1, IU2]>]>,
InstrItinData<IntDivW , [InstrStage<19, [IU1]>]>, InstrItinData<IIC_IntDivW , [InstrStage<19, [IU1]>]>,
InstrItinData<IntMFFS , [InstrStage<3, [FPU1]>]>, InstrItinData<IIC_IntMFFS , [InstrStage<3, [FPU1]>]>,
InstrItinData<IntMFVSCR , [InstrStage<1, [VIU1]>]>, InstrItinData<IIC_IntMFVSCR , [InstrStage<1, [VIU1]>]>,
InstrItinData<IntMTFSB0 , [InstrStage<3, [FPU1]>]>, InstrItinData<IIC_IntMTFSB0 , [InstrStage<3, [FPU1]>]>,
InstrItinData<IntMulHW , [InstrStage<5, [IU1]>]>, InstrItinData<IIC_IntMulHW , [InstrStage<5, [IU1]>]>,
InstrItinData<IntMulHWU , [InstrStage<6, [IU1]>]>, InstrItinData<IIC_IntMulHWU , [InstrStage<6, [IU1]>]>,
InstrItinData<IntMulLI , [InstrStage<3, [IU1]>]>, InstrItinData<IIC_IntMulLI , [InstrStage<3, [IU1]>]>,
InstrItinData<IntRotate , [InstrStage<1, [IU1, IU2]>]>, InstrItinData<IIC_IntRotate , [InstrStage<1, [IU1, IU2]>]>,
InstrItinData<IntShift , [InstrStage<1, [IU1, IU2]>]>, InstrItinData<IIC_IntShift , [InstrStage<1, [IU1, IU2]>]>,
InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2]>]>, InstrItinData<IIC_IntTrapW , [InstrStage<2, [IU1, IU2]>]>,
InstrItinData<BrB , [InstrStage<1, [BPU]>]>, InstrItinData<IIC_BrB , [InstrStage<1, [BPU]>]>,
InstrItinData<BrCR , [InstrStage<1, [SRU]>]>, InstrItinData<IIC_BrCR , [InstrStage<1, [SRU]>]>,
InstrItinData<BrMCR , [InstrStage<1, [SRU]>]>, InstrItinData<IIC_BrMCR , [InstrStage<1, [SRU]>]>,
InstrItinData<BrMCRX , [InstrStage<1, [SRU]>]>, InstrItinData<IIC_BrMCRX , [InstrStage<1, [SRU]>]>,
InstrItinData<LdStDCBF , [InstrStage<2, [SLU]>]>, InstrItinData<IIC_LdStDCBF , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStDCBI , [InstrStage<2, [SLU]>]>, InstrItinData<IIC_LdStDCBI , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLoad , [InstrStage<2, [SLU]>]>, InstrItinData<IIC_LdStLoad , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLoadUpd , [InstrStage<2, [SLU]>]>, InstrItinData<IIC_LdStLoadUpd , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStStore , [InstrStage<2, [SLU]>]>, InstrItinData<IIC_LdStStore , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStStoreUpd, [InstrStage<2, [SLU]>]>, InstrItinData<IIC_LdStStoreUpd, [InstrStage<2, [SLU]>]>,
InstrItinData<LdStDSS , [InstrStage<2, [SLU]>]>, InstrItinData<IIC_LdStDSS , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStICBI , [InstrStage<2, [SLU]>]>, InstrItinData<IIC_LdStICBI , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStSTFD , [InstrStage<2, [SLU]>]>, InstrItinData<IIC_LdStSTFD , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStSTFDU , [InstrStage<2, [SLU]>]>, InstrItinData<IIC_LdStSTFDU , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLFD , [InstrStage<2, [SLU]>]>, InstrItinData<IIC_LdStLFD , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLFDU , [InstrStage<2, [SLU]>]>, InstrItinData<IIC_LdStLFDU , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLHA , [InstrStage<2, [SLU]>]>, InstrItinData<IIC_LdStLHA , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLHAU , [InstrStage<2, [SLU]>]>, InstrItinData<IIC_LdStLHAU , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLMW , [InstrStage<34, [SLU]>]>, InstrItinData<IIC_LdStLMW , [InstrStage<34, [SLU]>]>,
InstrItinData<LdStLVecX , [InstrStage<2, [SLU]>]>, InstrItinData<IIC_LdStLVecX , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStLWARX , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStSTVEBX , [InstrStage<2, [SLU]>]>, InstrItinData<IIC_LdStSTVEBX , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStSTWCX , [InstrStage<5, [SLU]>]>, InstrItinData<IIC_LdStSTWCX , [InstrStage<5, [SLU]>]>,
InstrItinData<LdStSync , [InstrStage<8, [SLU]>]>, InstrItinData<IIC_LdStSync , [InstrStage<8, [SLU]>]>,
InstrItinData<SprISYNC , [InstrStage<2, [SRU]>]>, InstrItinData<IIC_SprISYNC , [InstrStage<2, [SRU]>]>,
InstrItinData<SprMFSR , [InstrStage<3, [SRU]>]>, InstrItinData<IIC_SprMFSR , [InstrStage<3, [SRU]>]>,
InstrItinData<SprMTMSR , [InstrStage<1, [SRU]>]>, InstrItinData<IIC_SprMTMSR , [InstrStage<1, [SRU]>]>,
InstrItinData<SprMTSR , [InstrStage<2, [SRU]>]>, InstrItinData<IIC_SprMTSR , [InstrStage<2, [SRU]>]>,
InstrItinData<SprTLBSYNC , [InstrStage<8, [SRU]>]>, InstrItinData<IIC_SprTLBSYNC , [InstrStage<8, [SRU]>]>,
InstrItinData<SprMFCR , [InstrStage<1, [SRU]>]>, InstrItinData<IIC_SprMFCR , [InstrStage<1, [SRU]>]>,
InstrItinData<SprMFMSR , [InstrStage<1, [SRU]>]>, InstrItinData<IIC_SprMFMSR , [InstrStage<1, [SRU]>]>,
InstrItinData<SprMFSPR , [InstrStage<3, [SRU]>]>, InstrItinData<IIC_SprMFSPR , [InstrStage<3, [SRU]>]>,
InstrItinData<SprMFTB , [InstrStage<1, [SRU]>]>, InstrItinData<IIC_SprMFTB , [InstrStage<1, [SRU]>]>,
InstrItinData<SprMTSPR , [InstrStage<2, [SRU]>]>, InstrItinData<IIC_SprMTSPR , [InstrStage<2, [SRU]>]>,
InstrItinData<SprMTSRIN , [InstrStage<2, [SRU]>]>, InstrItinData<IIC_SprMTSRIN , [InstrStage<2, [SRU]>]>,
InstrItinData<SprRFI , [InstrStage<2, [SRU]>]>, InstrItinData<IIC_SprRFI , [InstrStage<2, [SRU]>]>,
InstrItinData<SprSC , [InstrStage<2, [SRU]>]>, InstrItinData<IIC_SprSC , [InstrStage<2, [SRU]>]>,
InstrItinData<FPGeneral , [InstrStage<1, [FPU1]>]>, InstrItinData<IIC_FPGeneral , [InstrStage<1, [FPU1]>]>,
InstrItinData<FPAddSub , [InstrStage<1, [FPU1]>]>, InstrItinData<IIC_FPAddSub , [InstrStage<1, [FPU1]>]>,
InstrItinData<FPCompare , [InstrStage<1, [FPU1]>]>, InstrItinData<IIC_FPCompare , [InstrStage<1, [FPU1]>]>,
InstrItinData<FPDivD , [InstrStage<31, [FPU1]>]>, InstrItinData<IIC_FPDivD , [InstrStage<31, [FPU1]>]>,
InstrItinData<FPDivS , [InstrStage<17, [FPU1]>]>, InstrItinData<IIC_FPDivS , [InstrStage<17, [FPU1]>]>,
InstrItinData<FPFused , [InstrStage<1, [FPU1]>]>, InstrItinData<IIC_FPFused , [InstrStage<1, [FPU1]>]>,
InstrItinData<FPRes , [InstrStage<10, [FPU1]>]>, InstrItinData<IIC_FPRes , [InstrStage<10, [FPU1]>]>,
InstrItinData<VecGeneral , [InstrStage<1, [VIU1]>]>, InstrItinData<IIC_VecGeneral , [InstrStage<1, [VIU1]>]>,
InstrItinData<VecFP , [InstrStage<4, [VFPU]>]>, InstrItinData<IIC_VecFP , [InstrStage<4, [VFPU]>]>,
InstrItinData<VecFPCompare, [InstrStage<1, [VIU1]>]>, InstrItinData<IIC_VecFPCompare, [InstrStage<1, [VIU1]>]>,
InstrItinData<VecComplex , [InstrStage<3, [VIU2]>]>, InstrItinData<IIC_VecComplex , [InstrStage<3, [VIU2]>]>,
InstrItinData<VecPerm , [InstrStage<1, [VPU]>]>, InstrItinData<IIC_VecPerm , [InstrStage<1, [VPU]>]>,
InstrItinData<VecFPRound , [InstrStage<4, [VFPU]>]>, InstrItinData<IIC_VecFPRound , [InstrStage<4, [VFPU]>]>,
InstrItinData<VecVSL , [InstrStage<1, [VIU1]>]>, InstrItinData<IIC_VecVSL , [InstrStage<1, [VIU1]>]>,
InstrItinData<VecVSR , [InstrStage<1, [VIU1]>]> InstrItinData<IIC_VecVSR , [InstrStage<1, [VIU1]>]>
]>; ]>;

138
lib/Target/PowerPC/PPCScheduleG4Plus.td
View File

@@ -16,73 +16,73 @@ def IU4 : FuncUnit; // integer unit 4 (7450 simple)
def G4PlusItineraries : ProcessorItineraries< def G4PlusItineraries : ProcessorItineraries<
[IU1, IU2, IU3, IU4, BPU, SLU, FPU1, VFPU, VIU1, VIU2, VPU], [], [ [IU1, IU2, IU3, IU4, BPU, SLU, FPU1, VFPU, VIU1, VIU2, VPU], [], [
InstrItinData<IntSimple , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>, InstrItinData<IIC_IntSimple , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>, InstrItinData<IIC_IntGeneral , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>, InstrItinData<IIC_IntCompare , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
InstrItinData<IntDivW , [InstrStage<23, [IU2]>]>, InstrItinData<IIC_IntDivW , [InstrStage<23, [IU2]>]>,
InstrItinData<IntMFFS , [InstrStage<5, [FPU1]>]>, InstrItinData<IIC_IntMFFS , [InstrStage<5, [FPU1]>]>,
InstrItinData<IntMFVSCR , [InstrStage<2, [VFPU]>]>, InstrItinData<IIC_IntMFVSCR , [InstrStage<2, [VFPU]>]>,
InstrItinData<IntMTFSB0 , [InstrStage<5, [FPU1]>]>, InstrItinData<IIC_IntMTFSB0 , [InstrStage<5, [FPU1]>]>,
InstrItinData<IntMulHW , [InstrStage<4, [IU2]>]>, InstrItinData<IIC_IntMulHW , [InstrStage<4, [IU2]>]>,
InstrItinData<IntMulHWU , [InstrStage<4, [IU2]>]>, InstrItinData<IIC_IntMulHWU , [InstrStage<4, [IU2]>]>,
InstrItinData<IntMulLI , [InstrStage<3, [IU2]>]>, InstrItinData<IIC_IntMulLI , [InstrStage<3, [IU2]>]>,
InstrItinData<IntRotate , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>, InstrItinData<IIC_IntRotate , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
InstrItinData<IntShift , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>, InstrItinData<IIC_IntShift , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>,
InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>, InstrItinData<IIC_IntTrapW , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>,
InstrItinData<BrB , [InstrStage<1, [BPU]>]>, InstrItinData<IIC_BrB , [InstrStage<1, [BPU]>]>,
InstrItinData<BrCR , [InstrStage<2, [IU2]>]>, InstrItinData<IIC_BrCR , [InstrStage<2, [IU2]>]>,
InstrItinData<BrMCR , [InstrStage<2, [IU2]>]>, InstrItinData<IIC_BrMCR , [InstrStage<2, [IU2]>]>,
InstrItinData<BrMCRX , [InstrStage<2, [IU2]>]>, InstrItinData<IIC_BrMCRX , [InstrStage<2, [IU2]>]>,
InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStDCBF , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStDCBI , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStDCBI , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLoad , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStLoad , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLoadUpd , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStLoadUpd , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStStore , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStStore , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStStoreUpd, [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStStoreUpd, [InstrStage<3, [SLU]>]>,
InstrItinData<LdStDSS , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStDSS , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStICBI , [InstrStage<3, [IU2]>]>, InstrItinData<IIC_LdStICBI , [InstrStage<3, [IU2]>]>,
InstrItinData<LdStSTFD , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStSTFD , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStSTFDU , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStSTFDU , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLFD , [InstrStage<4, [SLU]>]>, InstrItinData<IIC_LdStLFD , [InstrStage<4, [SLU]>]>,
InstrItinData<LdStLFDU , [InstrStage<4, [SLU]>]>, InstrItinData<IIC_LdStLFDU , [InstrStage<4, [SLU]>]>,
InstrItinData<LdStLHA , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStLHA , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLHAU , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStLHAU , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLMW , [InstrStage<37, [SLU]>]>, InstrItinData<IIC_LdStLMW , [InstrStage<37, [SLU]>]>,
InstrItinData<LdStLVecX , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStLVecX , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLWA , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStLWA , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStLWARX , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStSTD , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStSTD , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStSTDCX , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStSTDCX , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStSTDU , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStSTDU , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStSTVEBX , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStSTVEBX , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStSTWCX , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStSTWCX , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStSync , [InstrStage<35, [SLU]>]>, InstrItinData<IIC_LdStSync , [InstrStage<35, [SLU]>]>,
InstrItinData<SprISYNC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>, InstrItinData<IIC_SprISYNC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>,
InstrItinData<SprMFSR , [InstrStage<4, [IU2]>]>, InstrItinData<IIC_SprMFSR , [InstrStage<4, [IU2]>]>,
InstrItinData<SprMTMSR , [InstrStage<2, [IU2]>]>, InstrItinData<IIC_SprMTMSR , [InstrStage<2, [IU2]>]>,
InstrItinData<SprMTSR , [InstrStage<2, [IU2]>]>, InstrItinData<IIC_SprMTSR , [InstrStage<2, [IU2]>]>,
InstrItinData<SprTLBSYNC , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_SprTLBSYNC , [InstrStage<3, [SLU]>]>,
InstrItinData<SprMFCR , [InstrStage<2, [IU2]>]>, InstrItinData<IIC_SprMFCR , [InstrStage<2, [IU2]>]>,
InstrItinData<SprMFMSR , [InstrStage<3, [IU2]>]>, InstrItinData<IIC_SprMFMSR , [InstrStage<3, [IU2]>]>,
InstrItinData<SprMFSPR , [InstrStage<4, [IU2]>]>, InstrItinData<IIC_SprMFSPR , [InstrStage<4, [IU2]>]>,
InstrItinData<SprMFTB , [InstrStage<5, [IU2]>]>, InstrItinData<IIC_SprMFTB , [InstrStage<5, [IU2]>]>,
InstrItinData<SprMTSPR , [InstrStage<2, [IU2]>]>, InstrItinData<IIC_SprMTSPR , [InstrStage<2, [IU2]>]>,
InstrItinData<SprMTSRIN , [InstrStage<2, [IU2]>]>, InstrItinData<IIC_SprMTSRIN , [InstrStage<2, [IU2]>]>,
InstrItinData<SprRFI , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>, InstrItinData<IIC_SprRFI , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
InstrItinData<SprSC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>, InstrItinData<IIC_SprSC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>,
InstrItinData<FPGeneral , [InstrStage<5, [FPU1]>]>, InstrItinData<IIC_FPGeneral , [InstrStage<5, [FPU1]>]>,
InstrItinData<FPAddSub , [InstrStage<5, [FPU1]>]>, InstrItinData<IIC_FPAddSub , [InstrStage<5, [FPU1]>]>,
InstrItinData<FPCompare , [InstrStage<5, [FPU1]>]>, InstrItinData<IIC_FPCompare , [InstrStage<5, [FPU1]>]>,
InstrItinData<FPDivD , [InstrStage<35, [FPU1]>]>, InstrItinData<IIC_FPDivD , [InstrStage<35, [FPU1]>]>,
InstrItinData<FPDivS , [InstrStage<21, [FPU1]>]>, InstrItinData<IIC_FPDivS , [InstrStage<21, [FPU1]>]>,
InstrItinData<FPFused , [InstrStage<5, [FPU1]>]>, InstrItinData<IIC_FPFused , [InstrStage<5, [FPU1]>]>,
InstrItinData<FPRes , [InstrStage<14, [FPU1]>]>, InstrItinData<IIC_FPRes , [InstrStage<14, [FPU1]>]>,
InstrItinData<VecGeneral , [InstrStage<1, [VIU1]>]>, InstrItinData<IIC_VecGeneral , [InstrStage<1, [VIU1]>]>,
InstrItinData<VecFP , [InstrStage<4, [VFPU]>]>, InstrItinData<IIC_VecFP , [InstrStage<4, [VFPU]>]>,
InstrItinData<VecFPCompare, [InstrStage<2, [VFPU]>]>, InstrItinData<IIC_VecFPCompare, [InstrStage<2, [VFPU]>]>,
InstrItinData<VecComplex , [InstrStage<4, [VIU2]>]>, InstrItinData<IIC_VecComplex , [InstrStage<4, [VIU2]>]>,
InstrItinData<VecPerm , [InstrStage<2, [VPU]>]>, InstrItinData<IIC_VecPerm , [InstrStage<2, [VPU]>]>,
InstrItinData<VecFPRound , [InstrStage<4, [VIU1]>]>, InstrItinData<IIC_VecFPRound , [InstrStage<4, [VIU1]>]>,
InstrItinData<VecVSL , [InstrStage<2, [VPU]>]>, InstrItinData<IIC_VecVSL , [InstrStage<2, [VPU]>]>,
InstrItinData<VecVSR , [InstrStage<2, [VPU]>]> InstrItinData<IIC_VecVSR , [InstrStage<2, [VPU]>]>
]>; ]>;

156
lib/Target/PowerPC/PPCScheduleG5.td
View File

@@ -13,84 +13,84 @@
def G5Itineraries : ProcessorItineraries< def G5Itineraries : ProcessorItineraries<
[IU1, IU2, SLU, BPU, FPU1, FPU2, VFPU, VIU1, VIU2, VPU], [], [ [IU1, IU2, SLU, BPU, FPU1, FPU2, VFPU, VIU1, VIU2, VPU], [], [
InstrItinData<IntSimple , [InstrStage<2, [IU1, IU2]>]>, InstrItinData<IIC_IntSimple , [InstrStage<2, [IU1, IU2]>]>,
InstrItinData<IntGeneral , [InstrStage<2, [IU1, IU2]>]>, InstrItinData<IIC_IntGeneral , [InstrStage<2, [IU1, IU2]>]>,
InstrItinData<IntCompare , [InstrStage<3, [IU1, IU2]>]>, InstrItinData<IIC_IntCompare , [InstrStage<3, [IU1, IU2]>]>,
InstrItinData<IntDivD , [InstrStage<68, [IU1]>]>, InstrItinData<IIC_IntDivD , [InstrStage<68, [IU1]>]>,
InstrItinData<IntDivW , [InstrStage<36, [IU1]>]>, InstrItinData<IIC_IntDivW , [InstrStage<36, [IU1]>]>,
InstrItinData<IntMFFS , [InstrStage<6, [IU2]>]>, InstrItinData<IIC_IntMFFS , [InstrStage<6, [IU2]>]>,
InstrItinData<IntMFVSCR , [InstrStage<1, [VFPU]>]>, InstrItinData<IIC_IntMFVSCR , [InstrStage<1, [VFPU]>]>,
InstrItinData<IntMTFSB0 , [InstrStage<6, [FPU1, FPU2]>]>, InstrItinData<IIC_IntMTFSB0 , [InstrStage<6, [FPU1, FPU2]>]>,
InstrItinData<IntMulHD , [InstrStage<7, [IU1, IU2]>]>, InstrItinData<IIC_IntMulHD , [InstrStage<7, [IU1, IU2]>]>,
InstrItinData<IntMulHW , [InstrStage<5, [IU1, IU2]>]>, InstrItinData<IIC_IntMulHW , [InstrStage<5, [IU1, IU2]>]>,
InstrItinData<IntMulHWU , [InstrStage<5, [IU1, IU2]>]>, InstrItinData<IIC_IntMulHWU , [InstrStage<5, [IU1, IU2]>]>,
InstrItinData<IntMulLI , [InstrStage<4, [IU1, IU2]>]>, InstrItinData<IIC_IntMulLI , [InstrStage<4, [IU1, IU2]>]>,
InstrItinData<IntRFID , [InstrStage<1, [IU2]>]>, InstrItinData<IIC_IntRFID , [InstrStage<1, [IU2]>]>,
InstrItinData<IntRotateD , [InstrStage<2, [IU1, IU2]>]>, InstrItinData<IIC_IntRotateD , [InstrStage<2, [IU1, IU2]>]>,
InstrItinData<IntRotateDI , [InstrStage<2, [IU1, IU2]>]>, InstrItinData<IIC_IntRotateDI , [InstrStage<2, [IU1, IU2]>]>,
InstrItinData<IntRotate , [InstrStage<4, [IU1, IU2]>]>, InstrItinData<IIC_IntRotate , [InstrStage<4, [IU1, IU2]>]>,
InstrItinData<IntShift , [InstrStage<2, [IU1, IU2]>]>, InstrItinData<IIC_IntShift , [InstrStage<2, [IU1, IU2]>]>,
InstrItinData<IntTrapD , [InstrStage<1, [IU1, IU2]>]>, InstrItinData<IIC_IntTrapD , [InstrStage<1, [IU1, IU2]>]>,
InstrItinData<IntTrapW , [InstrStage<1, [IU1, IU2]>]>, InstrItinData<IIC_IntTrapW , [InstrStage<1, [IU1, IU2]>]>,
InstrItinData<BrB , [InstrStage<1, [BPU]>]>, InstrItinData<IIC_BrB , [InstrStage<1, [BPU]>]>,
InstrItinData<BrCR , [InstrStage<4, [BPU]>]>, InstrItinData<IIC_BrCR , [InstrStage<4, [BPU]>]>,
InstrItinData<BrMCR , [InstrStage<2, [BPU]>]>, InstrItinData<IIC_BrMCR , [InstrStage<2, [BPU]>]>,
InstrItinData<BrMCRX , [InstrStage<3, [BPU]>]>, InstrItinData<IIC_BrMCRX , [InstrStage<3, [BPU]>]>,
InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStDCBF , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLoad , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStLoad , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLoadUpd , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStLoadUpd , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStStore , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStStore , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStStoreUpd, [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStStoreUpd, [InstrStage<3, [SLU]>]>,
InstrItinData<LdStDSS , [InstrStage<10, [SLU]>]>, InstrItinData<IIC_LdStDSS , [InstrStage<10, [SLU]>]>,
InstrItinData<LdStICBI , [InstrStage<40, [SLU]>]>, InstrItinData<IIC_LdStICBI , [InstrStage<40, [SLU]>]>,
InstrItinData<LdStSTFD , [InstrStage<4, [SLU]>]>, InstrItinData<IIC_LdStSTFD , [InstrStage<4, [SLU]>]>,
InstrItinData<LdStSTFDU , [InstrStage<4, [SLU]>]>, InstrItinData<IIC_LdStSTFDU , [InstrStage<4, [SLU]>]>,
InstrItinData<LdStLD , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStLD , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLDU , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStLDU , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLDARX , [InstrStage<11, [SLU]>]>, InstrItinData<IIC_LdStLDARX , [InstrStage<11, [SLU]>]>,
InstrItinData<LdStLFD , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStLFD , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLFDU , [InstrStage<5, [SLU]>]>, InstrItinData<IIC_LdStLFDU , [InstrStage<5, [SLU]>]>,
InstrItinData<LdStLHA , [InstrStage<5, [SLU]>]>, InstrItinData<IIC_LdStLHA , [InstrStage<5, [SLU]>]>,
InstrItinData<LdStLHAU , [InstrStage<5, [SLU]>]>, InstrItinData<IIC_LdStLHAU , [InstrStage<5, [SLU]>]>,
InstrItinData<LdStLMW , [InstrStage<64, [SLU]>]>, InstrItinData<IIC_LdStLMW , [InstrStage<64, [SLU]>]>,
InstrItinData<LdStLVecX , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStLVecX , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLWA , [InstrStage<5, [SLU]>]>, InstrItinData<IIC_LdStLWA , [InstrStage<5, [SLU]>]>,
InstrItinData<LdStLWARX , [InstrStage<11, [SLU]>]>, InstrItinData<IIC_LdStLWARX , [InstrStage<11, [SLU]>]>,
InstrItinData<LdStSLBIA , [InstrStage<40, [SLU]>]>, // needs work InstrItinData<IIC_LdStSLBIA , [InstrStage<40, [SLU]>]>, // needs work
InstrItinData<LdStSLBIE , [InstrStage<2, [SLU]>]>, InstrItinData<IIC_LdStSLBIE , [InstrStage<2, [SLU]>]>,
InstrItinData<LdStSTD , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStSTD , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStSTDU , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_LdStSTDU , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStSTDCX , [InstrStage<11, [SLU]>]>, InstrItinData<IIC_LdStSTDCX , [InstrStage<11, [SLU]>]>,
InstrItinData<LdStSTVEBX , [InstrStage<5, [SLU]>]>, InstrItinData<IIC_LdStSTVEBX , [InstrStage<5, [SLU]>]>,
InstrItinData<LdStSTWCX , [InstrStage<11, [SLU]>]>, InstrItinData<IIC_LdStSTWCX , [InstrStage<11, [SLU]>]>,
InstrItinData<LdStSync , [InstrStage<35, [SLU]>]>, InstrItinData<IIC_LdStSync , [InstrStage<35, [SLU]>]>,
InstrItinData<SprISYNC , [InstrStage<40, [SLU]>]>, // needs work InstrItinData<IIC_SprISYNC , [InstrStage<40, [SLU]>]>, // needs work
InstrItinData<SprMFSR , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_SprMFSR , [InstrStage<3, [SLU]>]>,
InstrItinData<SprMTMSR , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_SprMTMSR , [InstrStage<3, [SLU]>]>,
InstrItinData<SprMTSR , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_SprMTSR , [InstrStage<3, [SLU]>]>,
InstrItinData<SprTLBSYNC , [InstrStage<3, [SLU]>]>, InstrItinData<IIC_SprTLBSYNC , [InstrStage<3, [SLU]>]>,
InstrItinData<SprMFCR , [InstrStage<2, [IU2]>]>, InstrItinData<IIC_SprMFCR , [InstrStage<2, [IU2]>]>,
InstrItinData<SprMFMSR , [InstrStage<3, [IU2]>]>, InstrItinData<IIC_SprMFMSR , [InstrStage<3, [IU2]>]>,
InstrItinData<SprMFSPR , [InstrStage<3, [IU2]>]>, InstrItinData<IIC_SprMFSPR , [InstrStage<3, [IU2]>]>,
InstrItinData<SprMFTB , [InstrStage<10, [IU2]>]>, InstrItinData<IIC_SprMFTB , [InstrStage<10, [IU2]>]>,
InstrItinData<SprMTSPR , [InstrStage<8, [IU2]>]>, InstrItinData<IIC_SprMTSPR , [InstrStage<8, [IU2]>]>,
InstrItinData<SprSC , [InstrStage<1, [IU2]>]>, InstrItinData<IIC_SprSC , [InstrStage<1, [IU2]>]>,
InstrItinData<FPGeneral , [InstrStage<6, [FPU1, FPU2]>]>, InstrItinData<IIC_FPGeneral , [InstrStage<6, [FPU1, FPU2]>]>,
InstrItinData<FPAddSub , [InstrStage<6, [FPU1, FPU2]>]>, InstrItinData<IIC_FPAddSub , [InstrStage<6, [FPU1, FPU2]>]>,
InstrItinData<FPCompare , [InstrStage<8, [FPU1, FPU2]>]>, InstrItinData<IIC_FPCompare , [InstrStage<8, [FPU1, FPU2]>]>,
InstrItinData<FPDivD , [InstrStage<33, [FPU1, FPU2]>]>, InstrItinData<IIC_FPDivD , [InstrStage<33, [FPU1, FPU2]>]>,
InstrItinData<FPDivS , [InstrStage<33, [FPU1, FPU2]>]>, InstrItinData<IIC_FPDivS , [InstrStage<33, [FPU1, FPU2]>]>,
InstrItinData<FPFused , [InstrStage<6, [FPU1, FPU2]>]>, InstrItinData<IIC_FPFused , [InstrStage<6, [FPU1, FPU2]>]>,
InstrItinData<FPRes , [InstrStage<6, [FPU1, FPU2]>]>, InstrItinData<IIC_FPRes , [InstrStage<6, [FPU1, FPU2]>]>,
InstrItinData<FPSqrt , [InstrStage<40, [FPU1, FPU2]>]>, InstrItinData<IIC_FPSqrt , [InstrStage<40, [FPU1, FPU2]>]>,
InstrItinData<VecGeneral , [InstrStage<2, [VIU1]>]>, InstrItinData<IIC_VecGeneral , [InstrStage<2, [VIU1]>]>,
InstrItinData<VecFP , [InstrStage<8, [VFPU]>]>, InstrItinData<IIC_VecFP , [InstrStage<8, [VFPU]>]>,
InstrItinData<VecFPCompare, [InstrStage<2, [VFPU]>]>, InstrItinData<IIC_VecFPCompare, [InstrStage<2, [VFPU]>]>,
InstrItinData<VecComplex , [InstrStage<5, [VIU2]>]>, InstrItinData<IIC_VecComplex , [InstrStage<5, [VIU2]>]>,
InstrItinData<VecPerm , [InstrStage<3, [VPU]>]>, InstrItinData<IIC_VecPerm , [InstrStage<3, [VPU]>]>,
InstrItinData<VecFPRound , [InstrStage<8, [VFPU]>]>, InstrItinData<IIC_VecFPRound , [InstrStage<8, [VFPU]>]>,
InstrItinData<VecVSL , [InstrStage<2, [VIU1]>]>, InstrItinData<IIC_VecVSL , [InstrStage<2, [VIU1]>]>,
InstrItinData<VecVSR , [InstrStage<3, [VPU]>]> InstrItinData<IIC_VecVSR , [InstrStage<3, [VPU]>]>
]>; ]>;
// ===---------------------------------------------------------------------===// // ===---------------------------------------------------------------------===//