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[mips][microMIPS] This patch implements functionality in MIPS delay slot

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filler such as if delay slot filler have to put NOP instruction into the
delay slot of microMIPS BEQ or BNE instruction which uses the register $0,
then instead of emitting NOP this instruction is replaced by the corresponding
microMIPS compact branch instruction, i.e. BEQZC or BNEZC.

Differential Revision: http://reviews.llvm.org/D3566


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222580 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jozef Kolek
2014-11-21 22:04:35 +00:00
parent e83cdb9792
commit d9accc1e5f
5 changed files with 73 additions and 12 deletions
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2
test/CodeGen/Mips/micromips-atomic.ll
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@@ -14,5 +14,5 @@ entry:
; CHECK: ll $[[R1:[0-9]+]], 0($[[R0]])
; CHECK: addu $[[R2:[0-9]+]], $[[R1]], $4
; CHECK: sc $[[R2]], 0($[[R0]])
; CHECK: beqz $[[R2]], $[[BB0]]
; CHECK: beqzc $[[R2]], $[[BB0]]
}