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Avoid getting into an infinite loop when -disable-x86-shuffle-opti is specified.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30974 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2006-10-16 06:36:00 +00:00
parent 07e4b00a1a
commit d9b8e40ab3
1 changed files with 12 additions and 8 deletions
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20
lib/Target/X86/X86ISelLowering.cpp
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@@ -3413,7 +3413,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
// FIXME: we can do the same for v4f32 case when we know both parts of // FIXME: we can do the same for v4f32 case when we know both parts of
// the lower half come from scalar_to_vector (loadf32). We should do // the lower half come from scalar_to_vector (loadf32). We should do
// that in post legalizer dag combiner with target specific hooks. // that in post legalizer dag combiner with target specific hooks.
if (MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0) if (!NoShuffleOpti && MVT::isInteger(EVT) && (NonZeros & (0x3 << 2)) == 0)
return V[0]; return V[0];
MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems); MVT::ValueType MaskVT = MVT::getIntVectorWithNumElements(NumElems);
MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT); MVT::ValueType EVT = MVT::getVectorBaseType(MaskVT);
@@ -3466,6 +3466,8 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
unsigned NumElems = PermMask.getNumOperands(); unsigned NumElems = PermMask.getNumOperands();
bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; bool V1IsUndef = V1.getOpcode() == ISD::UNDEF;
bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; bool V2IsUndef = V2.getOpcode() == ISD::UNDEF;
bool V1IsSplat = false;
bool V2IsSplat = false;
if (isUndefShuffle(Op.Val)) if (isUndefShuffle(Op.Val))
return DAG.getNode(ISD::UNDEF, VT); return DAG.getNode(ISD::UNDEF, VT);
@@ -3492,8 +3494,8 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val)) ShouldXformToMOVLP(V1.Val, V2.Val, PermMask.Val))
return CommuteVectorShuffle(Op, DAG); return CommuteVectorShuffle(Op, DAG);
bool V1IsSplat = isSplatVector(V1.Val); V1IsSplat = isSplatVector(V1.Val);
bool V2IsSplat = isSplatVector(V2.Val); V2IsSplat = isSplatVector(V2.Val);
if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) {
Op = CommuteVectorShuffle(Op, DAG); Op = CommuteVectorShuffle(Op, DAG);
V1 = Op.getOperand(0); V1 = Op.getOperand(0);
@@ -3519,12 +3521,14 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
} }
return Op; return Op;
} }
}
if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) || if (X86::isUNPCKL_v_undef_Mask(PermMask.Val) ||
X86::isUNPCKLMask(PermMask.Val) || X86::isUNPCKLMask(PermMask.Val) ||
X86::isUNPCKHMask(PermMask.Val)) X86::isUNPCKHMask(PermMask.Val))
return Op; return Op;
if (!NoShuffleOpti) {
if (V2IsSplat) { if (V2IsSplat) {
// Normalize mask so all entries that point to V2 points to its first // Normalize mask so all entries that point to V2 points to its first
// element then try to match unpck{h|l} again. If match, return a // element then try to match unpck{h|l} again. If match, return a
@@ -3543,7 +3547,7 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
} }
// Normalize the node to match x86 shuffle ops if needed // Normalize the node to match x86 shuffle ops if needed
if (V2.getOpcode() != ISD::UNDEF) if (!NoShuffleOpti && V2.getOpcode() != ISD::UNDEF)
if (isCommutedSHUFP(PermMask.Val)) { if (isCommutedSHUFP(PermMask.Val)) {
Op = CommuteVectorShuffle(Op, DAG); Op = CommuteVectorShuffle(Op, DAG);
V1 = Op.getOperand(0); V1 = Op.getOperand(0);