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This target does not support/want ISD::BRCONDTWOWAY

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21164 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-04-09 03:22:37 +00:00
parent 644db4ec5f
commit da4d4694a8
3 changed files with 3 additions and 0 deletions
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1
lib/Target/Alpha/AlphaISelPattern.cpp
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@ -62,6 +62,7 @@ namespace {
addRegisterClass(MVT::f64, Alpha::FPRCRegisterClass);
addRegisterClass(MVT::f32, Alpha::FPRCRegisterClass);
setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
setOperationAction(ISD::EXTLOAD , MVT::i1 , Promote);
setOperationAction(ISD::EXTLOAD , MVT::f32 , Promote);

1
lib/Target/IA64/IA64ISelPattern.cpp
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@ -55,6 +55,7 @@ namespace {
// register class for predicate registers
addRegisterClass(MVT::i1, IA64::PRRegisterClass);
setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
setSetCCResultType(MVT::i1);

1
lib/Target/X86/X86ISelPattern.cpp
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@ -56,6 +56,7 @@ namespace {
// well.
/**/ addRegisterClass(MVT::i1, X86::R8RegisterClass);
setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
setOperationAction(ISD::ZERO_EXTEND_INREG, MVT::i16 , Expand);