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Various cleanups to this pass, no functionality change

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24846 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2005-12-19 00:46:20 +00:00
parent f53d0bfbfd
commit da5a7fd8d4
2 changed files with 86 additions and 92 deletions
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89
lib/Target/Sparc/FPMover.cpp
View File

@@ -7,7 +7,7 @@
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// Turns FpMOVD instructions into FMOVS pairs after regalloc. // Expand FpMOVD/FpABSD/FpNEGD instructions into their single-precision pieces.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@@ -19,8 +19,8 @@
using namespace llvm; using namespace llvm;
namespace { namespace {
Statistic<> NumFpMOVDs ("fpmover", "# FpMOVD instructions translated"); Statistic<> NumFpDs("fpmover", "Number of instructions translated");
Statistic<> SkippedFpMOVDs ("fpmover", "# FpMOVD instructions skipped"); Statistic<> NoopFpDs("fpmover", "Number of noop instructions removed");
struct FPMover : public MachineFunctionPass { struct FPMover : public MachineFunctionPass {
/// Target machine description which we query for reg. names, data /// Target machine description which we query for reg. names, data
@@ -28,18 +28,18 @@ namespace {
/// ///
TargetMachine &TM; TargetMachine &TM;
FPMover (TargetMachine &tm) : TM (tm) { } FPMover(TargetMachine &tm) : TM(tm) { }
virtual const char *getPassName () const { virtual const char *getPassName() const {
return "SparcV8 Double-FP Move Fixer"; return "SparcV8 Double-FP Move Fixer";
} }
bool runOnMachineBasicBlock (MachineBasicBlock &MBB); bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
bool runOnMachineFunction (MachineFunction &F) { bool runOnMachineFunction(MachineFunction &F) {
bool Changed = false; bool Changed = false;
for (MachineFunction::iterator FI = F.begin (), FE = F.end (); for (MachineFunction::iterator FI = F.begin(), FE = F.end();
FI != FE; ++FI) FI != FE; ++FI)
Changed |= runOnMachineBasicBlock (*FI); Changed |= runOnMachineBasicBlock(*FI);
return Changed; return Changed;
} }
@@ -49,66 +49,63 @@ namespace {
/// createSparcV8FPMoverPass - Returns a pass that turns FpMOVD /// createSparcV8FPMoverPass - Returns a pass that turns FpMOVD
/// instructions into FMOVS instructions /// instructions into FMOVS instructions
/// ///
FunctionPass *llvm::createSparcV8FPMoverPass (TargetMachine &tm) { FunctionPass *llvm::createSparcV8FPMoverPass(TargetMachine &tm) {
return new FPMover (tm); return new FPMover(tm);
} }
static void doubleToSingleRegPair(unsigned doubleReg, unsigned &singleReg1, /// getDoubleRegPair - Given a DFP register, return the even and odd FP
unsigned &singleReg2) { /// registers that correspond to it.
const unsigned EvenHalvesOfPairs[] = { static void getDoubleRegPair(unsigned DoubleReg, unsigned &EvenReg,
unsigned &OddReg) {
static const unsigned EvenHalvesOfPairs[] = {
V8::F0, V8::F2, V8::F4, V8::F6, V8::F8, V8::F10, V8::F12, V8::F14, V8::F0, V8::F2, V8::F4, V8::F6, V8::F8, V8::F10, V8::F12, V8::F14,
V8::F16, V8::F18, V8::F20, V8::F22, V8::F24, V8::F26, V8::F28, V8::F30 V8::F16, V8::F18, V8::F20, V8::F22, V8::F24, V8::F26, V8::F28, V8::F30
}; };
const unsigned OddHalvesOfPairs[] = { static const unsigned OddHalvesOfPairs[] = {
V8::F1, V8::F3, V8::F5, V8::F7, V8::F9, V8::F11, V8::F13, V8::F15, V8::F1, V8::F3, V8::F5, V8::F7, V8::F9, V8::F11, V8::F13, V8::F15,
V8::F17, V8::F19, V8::F21, V8::F23, V8::F25, V8::F27, V8::F29, V8::F31 V8::F17, V8::F19, V8::F21, V8::F23, V8::F25, V8::F27, V8::F29, V8::F31
}; };
const unsigned DoubleRegsInOrder[] = { static const unsigned DoubleRegsInOrder[] = {
V8::D0, V8::D1, V8::D2, V8::D3, V8::D4, V8::D5, V8::D6, V8::D7, V8::D8, V8::D0, V8::D1, V8::D2, V8::D3, V8::D4, V8::D5, V8::D6, V8::D7, V8::D8,
V8::D9, V8::D10, V8::D11, V8::D12, V8::D13, V8::D14, V8::D15 V8::D9, V8::D10, V8::D11, V8::D12, V8::D13, V8::D14, V8::D15
}; };
for (unsigned i = 0; i < sizeof(DoubleRegsInOrder)/sizeof(unsigned); ++i) for (unsigned i = 0; i < sizeof(DoubleRegsInOrder)/sizeof(unsigned); ++i)
if (DoubleRegsInOrder[i] == doubleReg) { if (DoubleRegsInOrder[i] == DoubleReg) {
singleReg1 = EvenHalvesOfPairs[i]; EvenReg = EvenHalvesOfPairs[i];
singleReg2 = OddHalvesOfPairs[i]; OddReg = OddHalvesOfPairs[i];
return; return;
} }
assert (0 && "Can't find reg"); assert(0 && "Can't find reg");
} }
/// runOnMachineBasicBlock - Fixup FpMOVD instructions in this MBB. /// runOnMachineBasicBlock - Fixup FpMOVD instructions in this MBB.
/// ///
bool FPMover::runOnMachineBasicBlock (MachineBasicBlock &MBB) { bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
bool Changed = false; bool Changed = false;
for (MachineBasicBlock::iterator I = MBB.begin (); I != MBB.end (); ++I) for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
if (V8::FpMOVD == I->getOpcode ()) { MachineInstr *MI = I++;
unsigned NewSrcReg0 = 0, NewSrcReg1 = 0, NewDestReg0 = 0, NewDestReg1 = 0; if (MI->getOpcode() == V8::FpMOVD) {
doubleToSingleRegPair (I->getOperand (0).getReg (), NewDestReg0, unsigned DestDReg = MI->getOperand(0).getReg();
NewDestReg1); unsigned SrcDReg = MI->getOperand(1).getReg();
doubleToSingleRegPair (I->getOperand (1).getReg (), NewSrcReg0, if (DestDReg != SrcDReg || MI->getOpcode() != V8::FpMOVD) {
NewSrcReg1); unsigned EvenSrcReg = 0, OddSrcReg = 0, EvenDestReg = 0, OddDestReg = 0;
MachineBasicBlock::iterator J = I; getDoubleRegPair(DestDReg, EvenDestReg, OddDestReg);
++J; getDoubleRegPair(SrcDReg, EvenSrcReg, OddSrcReg);
if (!(NewDestReg0 == NewSrcReg0 && NewDestReg1 == NewSrcReg1)) {
I->setOpcode (V8::FMOVS); I->setOpcode(V8::FMOVS);
I->SetMachineOperandReg (0, NewDestReg0); I->SetMachineOperandReg(0, EvenDestReg);
I->SetMachineOperandReg (1, NewSrcReg0); I->SetMachineOperandReg(1, EvenSrcReg);
DEBUG (std::cerr << "FPMover: new dest reg. is: " << NewDestReg0 DEBUG(std::cerr << "FPMover: the modified instr is: " << *I);
<< "; modified instr is: " << *I);
// Insert copy for the other half of the double: // Insert copy for the other half of the double:
MachineInstr *MI2 = MI = BuildMI(MBB, I, V8::FMOVS, 1, OddDestReg).addReg(OddSrcReg);
BuildMI (MBB, J, V8::FMOVS, 1, NewDestReg1).addReg (NewSrcReg1); DEBUG(std::cerr << "FPMover: the inserted instr is: " << *MI);
DEBUG (std::cerr << "FPMover: new dest reg. is " << NewDestReg1 ++NumFpDs;
<< "; inserted instr is: " << *MI2);
++NumFpMOVDs;
I = J;
--I;
} else { } else {
MBB.erase (I); MBB.erase(MI);
++SkippedFpMOVDs; ++NoopFpDs;
I = J;
} }
Changed = true; Changed = true;
} }
}
return Changed; return Changed;
} }

89
lib/Target/SparcV8/FPMover.cpp
View File

@@ -7,7 +7,7 @@
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// Turns FpMOVD instructions into FMOVS pairs after regalloc. // Expand FpMOVD/FpABSD/FpNEGD instructions into their single-precision pieces.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@@ -19,8 +19,8 @@
using namespace llvm; using namespace llvm;
namespace { namespace {
Statistic<> NumFpMOVDs ("fpmover", "# FpMOVD instructions translated"); Statistic<> NumFpDs("fpmover", "Number of instructions translated");
Statistic<> SkippedFpMOVDs ("fpmover", "# FpMOVD instructions skipped"); Statistic<> NoopFpDs("fpmover", "Number of noop instructions removed");
struct FPMover : public MachineFunctionPass { struct FPMover : public MachineFunctionPass {
/// Target machine description which we query for reg. names, data /// Target machine description which we query for reg. names, data
@@ -28,18 +28,18 @@ namespace {
/// ///
TargetMachine &TM; TargetMachine &TM;
FPMover (TargetMachine &tm) : TM (tm) { } FPMover(TargetMachine &tm) : TM(tm) { }
virtual const char *getPassName () const { virtual const char *getPassName() const {
return "SparcV8 Double-FP Move Fixer"; return "SparcV8 Double-FP Move Fixer";
} }
bool runOnMachineBasicBlock (MachineBasicBlock &MBB); bool runOnMachineBasicBlock(MachineBasicBlock &MBB);
bool runOnMachineFunction (MachineFunction &F) { bool runOnMachineFunction(MachineFunction &F) {
bool Changed = false; bool Changed = false;
for (MachineFunction::iterator FI = F.begin (), FE = F.end (); for (MachineFunction::iterator FI = F.begin(), FE = F.end();
FI != FE; ++FI) FI != FE; ++FI)
Changed |= runOnMachineBasicBlock (*FI); Changed |= runOnMachineBasicBlock(*FI);
return Changed; return Changed;
} }
@@ -49,66 +49,63 @@ namespace {
/// createSparcV8FPMoverPass - Returns a pass that turns FpMOVD /// createSparcV8FPMoverPass - Returns a pass that turns FpMOVD
/// instructions into FMOVS instructions /// instructions into FMOVS instructions
/// ///
FunctionPass *llvm::createSparcV8FPMoverPass (TargetMachine &tm) { FunctionPass *llvm::createSparcV8FPMoverPass(TargetMachine &tm) {
return new FPMover (tm); return new FPMover(tm);
} }
static void doubleToSingleRegPair(unsigned doubleReg, unsigned &singleReg1, /// getDoubleRegPair - Given a DFP register, return the even and odd FP
unsigned &singleReg2) { /// registers that correspond to it.
const unsigned EvenHalvesOfPairs[] = { static void getDoubleRegPair(unsigned DoubleReg, unsigned &EvenReg,
unsigned &OddReg) {
static const unsigned EvenHalvesOfPairs[] = {
V8::F0, V8::F2, V8::F4, V8::F6, V8::F8, V8::F10, V8::F12, V8::F14, V8::F0, V8::F2, V8::F4, V8::F6, V8::F8, V8::F10, V8::F12, V8::F14,
V8::F16, V8::F18, V8::F20, V8::F22, V8::F24, V8::F26, V8::F28, V8::F30 V8::F16, V8::F18, V8::F20, V8::F22, V8::F24, V8::F26, V8::F28, V8::F30
}; };
const unsigned OddHalvesOfPairs[] = { static const unsigned OddHalvesOfPairs[] = {
V8::F1, V8::F3, V8::F5, V8::F7, V8::F9, V8::F11, V8::F13, V8::F15, V8::F1, V8::F3, V8::F5, V8::F7, V8::F9, V8::F11, V8::F13, V8::F15,
V8::F17, V8::F19, V8::F21, V8::F23, V8::F25, V8::F27, V8::F29, V8::F31 V8::F17, V8::F19, V8::F21, V8::F23, V8::F25, V8::F27, V8::F29, V8::F31
}; };
const unsigned DoubleRegsInOrder[] = { static const unsigned DoubleRegsInOrder[] = {
V8::D0, V8::D1, V8::D2, V8::D3, V8::D4, V8::D5, V8::D6, V8::D7, V8::D8, V8::D0, V8::D1, V8::D2, V8::D3, V8::D4, V8::D5, V8::D6, V8::D7, V8::D8,
V8::D9, V8::D10, V8::D11, V8::D12, V8::D13, V8::D14, V8::D15 V8::D9, V8::D10, V8::D11, V8::D12, V8::D13, V8::D14, V8::D15
}; };
for (unsigned i = 0; i < sizeof(DoubleRegsInOrder)/sizeof(unsigned); ++i) for (unsigned i = 0; i < sizeof(DoubleRegsInOrder)/sizeof(unsigned); ++i)
if (DoubleRegsInOrder[i] == doubleReg) { if (DoubleRegsInOrder[i] == DoubleReg) {
singleReg1 = EvenHalvesOfPairs[i]; EvenReg = EvenHalvesOfPairs[i];
singleReg2 = OddHalvesOfPairs[i]; OddReg = OddHalvesOfPairs[i];
return; return;
} }
assert (0 && "Can't find reg"); assert(0 && "Can't find reg");
} }
/// runOnMachineBasicBlock - Fixup FpMOVD instructions in this MBB. /// runOnMachineBasicBlock - Fixup FpMOVD instructions in this MBB.
/// ///
bool FPMover::runOnMachineBasicBlock (MachineBasicBlock &MBB) { bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
bool Changed = false; bool Changed = false;
for (MachineBasicBlock::iterator I = MBB.begin (); I != MBB.end (); ++I) for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ) {
if (V8::FpMOVD == I->getOpcode ()) { MachineInstr *MI = I++;
unsigned NewSrcReg0 = 0, NewSrcReg1 = 0, NewDestReg0 = 0, NewDestReg1 = 0; if (MI->getOpcode() == V8::FpMOVD) {
doubleToSingleRegPair (I->getOperand (0).getReg (), NewDestReg0, unsigned DestDReg = MI->getOperand(0).getReg();
NewDestReg1); unsigned SrcDReg = MI->getOperand(1).getReg();
doubleToSingleRegPair (I->getOperand (1).getReg (), NewSrcReg0, if (DestDReg != SrcDReg || MI->getOpcode() != V8::FpMOVD) {
NewSrcReg1); unsigned EvenSrcReg = 0, OddSrcReg = 0, EvenDestReg = 0, OddDestReg = 0;
MachineBasicBlock::iterator J = I; getDoubleRegPair(DestDReg, EvenDestReg, OddDestReg);
++J; getDoubleRegPair(SrcDReg, EvenSrcReg, OddSrcReg);
if (!(NewDestReg0 == NewSrcReg0 && NewDestReg1 == NewSrcReg1)) {
I->setOpcode (V8::FMOVS); I->setOpcode(V8::FMOVS);
I->SetMachineOperandReg (0, NewDestReg0); I->SetMachineOperandReg(0, EvenDestReg);
I->SetMachineOperandReg (1, NewSrcReg0); I->SetMachineOperandReg(1, EvenSrcReg);
DEBUG (std::cerr << "FPMover: new dest reg. is: " << NewDestReg0 DEBUG(std::cerr << "FPMover: the modified instr is: " << *I);
<< "; modified instr is: " << *I);
// Insert copy for the other half of the double: // Insert copy for the other half of the double:
MachineInstr *MI2 = MI = BuildMI(MBB, I, V8::FMOVS, 1, OddDestReg).addReg(OddSrcReg);
BuildMI (MBB, J, V8::FMOVS, 1, NewDestReg1).addReg (NewSrcReg1); DEBUG(std::cerr << "FPMover: the inserted instr is: " << *MI);
DEBUG (std::cerr << "FPMover: new dest reg. is " << NewDestReg1 ++NumFpDs;
<< "; inserted instr is: " << *MI2);
++NumFpMOVDs;
I = J;
--I;
} else { } else {
MBB.erase (I); MBB.erase(MI);
++SkippedFpMOVDs; ++NoopFpDs;
I = J;
} }
Changed = true; Changed = true;
} }
}
return Changed; return Changed;
} }