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MC: Modernize MCOperand API naming. NFC.

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MCOperand::Create*() methods renamed to MCOperand::create*().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237275 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2015-05-13 18:37:00 +00:00
parent 428e9d7608
commit db703aaedd
55 changed files with 1190 additions and 1191 deletions
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302
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@@ -582,12 +582,12 @@ static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
if (I == MI.end()) break;
if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
if (i > 0 && OpInfo[i-1].isPredicate()) continue;
MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
return;
}
}
MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
}
// Most Thumb instructions don't have explicit predicates in the
@@ -646,22 +646,22 @@ ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
for (unsigned i = 0; i < NumOps; ++i, ++I) {
if (I == MI.end()) break;
if (OpInfo[i].isPredicate()) {
I = MI.insert(I, MCOperand::CreateImm(CC));
I = MI.insert(I, MCOperand::createImm(CC));
++I;
if (CC == ARMCC::AL)
MI.insert(I, MCOperand::CreateReg(0));
MI.insert(I, MCOperand::createReg(0));
else
MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
MI.insert(I, MCOperand::createReg(ARM::CPSR));
return S;
}
}
I = MI.insert(I, MCOperand::CreateImm(CC));
I = MI.insert(I, MCOperand::createImm(CC));
++I;
if (CC == ARMCC::AL)
MI.insert(I, MCOperand::CreateReg(0));
MI.insert(I, MCOperand::createReg(0));
else
MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
MI.insert(I, MCOperand::createReg(ARM::CPSR));
return S;
}
@@ -894,7 +894,7 @@ static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
return MCDisassembler::Fail;
unsigned Register = GPRDecoderTable[RegNo];
Inst.addOperand(MCOperand::CreateReg(Register));
Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
@@ -918,7 +918,7 @@ DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
if (RegNo == 15)
{
Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
return MCDisassembler::Success;
}
@@ -949,7 +949,7 @@ static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
S = MCDisassembler::SoftFail;
unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
Inst.addOperand(MCOperand::CreateReg(RegisterPair));
Inst.addOperand(MCOperand::createReg(RegisterPair));
return S;
}
@@ -979,7 +979,7 @@ static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
return MCDisassembler::Fail;
}
Inst.addOperand(MCOperand::CreateReg(Register));
Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
@@ -1009,7 +1009,7 @@ static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
return MCDisassembler::Fail;
unsigned Register = SPRDecoderTable[RegNo];
Inst.addOperand(MCOperand::CreateReg(Register));
Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
@@ -1034,7 +1034,7 @@ static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
return MCDisassembler::Fail;
unsigned Register = DPRDecoderTable[RegNo];
Inst.addOperand(MCOperand::CreateReg(Register));
Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
@@ -1068,7 +1068,7 @@ static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
RegNo >>= 1;
unsigned Register = QPRDecoderTable[RegNo];
Inst.addOperand(MCOperand::CreateReg(Register));
Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
@@ -1087,7 +1087,7 @@ static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
return MCDisassembler::Fail;
unsigned Register = DPairDecoderTable[RegNo];
Inst.addOperand(MCOperand::CreateReg(Register));
Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
@@ -1110,7 +1110,7 @@ static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
return MCDisassembler::Fail;
unsigned Register = DPairSpacedDecoderTable[RegNo];
Inst.addOperand(MCOperand::CreateReg(Register));
Inst.addOperand(MCOperand::createReg(Register));
return MCDisassembler::Success;
}
@@ -1120,20 +1120,20 @@ static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
// AL predicate is not allowed on Thumb1 branches.
if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(Val));
Inst.addOperand(MCOperand::createImm(Val));
if (Val == ARMCC::AL) {
Inst.addOperand(MCOperand::CreateReg(0));
Inst.addOperand(MCOperand::createReg(0));
} else
Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
Inst.addOperand(MCOperand::createReg(ARM::CPSR));
return MCDisassembler::Success;
}
static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
if (Val)
Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
Inst.addOperand(MCOperand::createReg(ARM::CPSR));
else
Inst.addOperand(MCOperand::CreateReg(0));
Inst.addOperand(MCOperand::createReg(0));
return MCDisassembler::Success;
}
@@ -1169,7 +1169,7 @@ static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
Shift = ARM_AM::rrx;
unsigned Op = Shift | (imm << 3);
Inst.addOperand(MCOperand::CreateImm(Op));
Inst.addOperand(MCOperand::createImm(Op));
return S;
}
@@ -1204,7 +1204,7 @@ static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
break;
}
Inst.addOperand(MCOperand::CreateImm(Shift));
Inst.addOperand(MCOperand::createImm(Shift));
return S;
}
@@ -1318,7 +1318,7 @@ static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
uint32_t lsb_mask = (1U << lsb) - 1;
Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
return S;
}
@@ -1378,8 +1378,8 @@ static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
if ((featureBits & ARM::HasV8Ops) && (coproc != 14))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(coproc));
Inst.addOperand(MCOperand::CreateImm(CRd));
Inst.addOperand(MCOperand::createImm(coproc));
Inst.addOperand(MCOperand::createImm(CRd));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
@@ -1417,7 +1417,7 @@ static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
case ARM::STC_PRE:
case ARM::STCL_PRE:
imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
Inst.addOperand(MCOperand::CreateImm(imm));
Inst.addOperand(MCOperand::createImm(imm));
break;
case ARM::t2LDC2_POST:
case ARM::t2LDC2L_POST:
@@ -1440,7 +1440,7 @@ static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
default:
// The 'option' variant doesn't encode 'U' in the immediate since
// the immediate is unsigned [0,255].
Inst.addOperand(MCOperand::CreateImm(imm));
Inst.addOperand(MCOperand::createImm(imm));
break;
}
@@ -1564,11 +1564,11 @@ DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
Opc = ARM_AM::rrx;
unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
Inst.addOperand(MCOperand::CreateImm(imm));
Inst.addOperand(MCOperand::createImm(imm));
} else {
Inst.addOperand(MCOperand::CreateReg(0));
Inst.addOperand(MCOperand::createReg(0));
unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
Inst.addOperand(MCOperand::CreateImm(tmp));
Inst.addOperand(MCOperand::createImm(tmp));
}
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
@@ -1615,7 +1615,7 @@ static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
else
shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
Inst.addOperand(MCOperand::CreateImm(shift));
Inst.addOperand(MCOperand::createImm(shift));
return S;
}
@@ -1798,12 +1798,12 @@ DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
return MCDisassembler::Fail;
if (type) {
Inst.addOperand(MCOperand::CreateReg(0));
Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
Inst.addOperand(MCOperand::createReg(0));
Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
} else {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(U));
Inst.addOperand(MCOperand::createImm(U));
}
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
@@ -1834,7 +1834,7 @@ static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
break;
}
Inst.addOperand(MCOperand::CreateImm(mode));
Inst.addOperand(MCOperand::createImm(mode));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
@@ -1936,7 +1936,7 @@ static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
return MCDisassembler::Fail;
Inst.addOperand(
MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
return S;
}
@@ -1980,22 +1980,22 @@ static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
if (imod && M) {
Inst.setOpcode(ARM::CPS3p);
Inst.addOperand(MCOperand::CreateImm(imod));
Inst.addOperand(MCOperand::CreateImm(iflags));
Inst.addOperand(MCOperand::CreateImm(mode));
Inst.addOperand(MCOperand::createImm(imod));
Inst.addOperand(MCOperand::createImm(iflags));
Inst.addOperand(MCOperand::createImm(mode));
} else if (imod && !M) {
Inst.setOpcode(ARM::CPS2p);
Inst.addOperand(MCOperand::CreateImm(imod));
Inst.addOperand(MCOperand::CreateImm(iflags));
Inst.addOperand(MCOperand::createImm(imod));
Inst.addOperand(MCOperand::createImm(iflags));
if (mode) S = MCDisassembler::SoftFail;
} else if (!imod && M) {
Inst.setOpcode(ARM::CPS1p);
Inst.addOperand(MCOperand::CreateImm(mode));
Inst.addOperand(MCOperand::createImm(mode));
if (iflags) S = MCDisassembler::SoftFail;
} else {
// imod == '00' && M == '0' --> UNPREDICTABLE
Inst.setOpcode(ARM::CPS1p);
Inst.addOperand(MCOperand::CreateImm(mode));
Inst.addOperand(MCOperand::createImm(mode));
S = MCDisassembler::SoftFail;
}
@@ -2020,17 +2020,17 @@ static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
if (imod && M) {
Inst.setOpcode(ARM::t2CPS3p);
Inst.addOperand(MCOperand::CreateImm(imod));
Inst.addOperand(MCOperand::CreateImm(iflags));
Inst.addOperand(MCOperand::CreateImm(mode));
Inst.addOperand(MCOperand::createImm(imod));
Inst.addOperand(MCOperand::createImm(iflags));
Inst.addOperand(MCOperand::createImm(mode));
} else if (imod && !M) {
Inst.setOpcode(ARM::t2CPS2p);
Inst.addOperand(MCOperand::CreateImm(imod));
Inst.addOperand(MCOperand::CreateImm(iflags));
Inst.addOperand(MCOperand::createImm(imod));
Inst.addOperand(MCOperand::createImm(iflags));
if (mode) S = MCDisassembler::SoftFail;
} else if (!imod && M) {
Inst.setOpcode(ARM::t2CPS1p);
Inst.addOperand(MCOperand::CreateImm(mode));
Inst.addOperand(MCOperand::createImm(mode));
if (iflags) S = MCDisassembler::SoftFail;
} else {
// imod == '00' && M == '0' --> this is a HINT instruction
@@ -2038,7 +2038,7 @@ static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
// HINT are defined only for immediate in [0..4]
if(imm > 4) return MCDisassembler::Fail;
Inst.setOpcode(ARM::t2HINT);
Inst.addOperand(MCOperand::CreateImm(imm));
Inst.addOperand(MCOperand::createImm(imm));
}
return S;
@@ -2063,7 +2063,7 @@ static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
return MCDisassembler::Fail;
if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
Inst.addOperand(MCOperand::CreateImm(imm));
Inst.addOperand(MCOperand::createImm(imm));
return S;
}
@@ -2087,7 +2087,7 @@ static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
return MCDisassembler::Fail;
if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
Inst.addOperand(MCOperand::CreateImm(imm));
Inst.addOperand(MCOperand::createImm(imm));
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
return MCDisassembler::Fail;
@@ -2166,7 +2166,7 @@ static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
S = MCDisassembler::SoftFail;
Inst.setOpcode(ARM::SETPAN);
Inst.addOperand(MCOperand::CreateImm(Imm));
Inst.addOperand(MCOperand::createImm(Imm));
return S;
}
@@ -2184,7 +2184,7 @@ static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
if (!add) imm *= -1;
if (imm == 0 && !add) imm = INT32_MIN;
Inst.addOperand(MCOperand::CreateImm(imm));
Inst.addOperand(MCOperand::createImm(imm));
if (Rn == 15)
tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
@@ -2203,9 +2203,9 @@ static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
return MCDisassembler::Fail;
if (U)
Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
else
Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
return S;
}
@@ -2237,7 +2237,7 @@ DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
int imm32 = SignExtend32<25>(tmp << 1);
if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
true, 4, Inst, Decoder))
Inst.addOperand(MCOperand::CreateImm(imm32));
Inst.addOperand(MCOperand::createImm(imm32));
return Status;
}
@@ -2255,13 +2255,13 @@ DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
imm |= fieldFromInstruction(Insn, 24, 1) << 1;
if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
true, 4, Inst, Decoder))
Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
return S;
}
if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
true, 4, Inst, Decoder))
Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
return MCDisassembler::Fail;
@@ -2279,9 +2279,9 @@ static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
if (!align)
Inst.addOperand(MCOperand::CreateImm(0));
Inst.addOperand(MCOperand::createImm(0));
else
Inst.addOperand(MCOperand::CreateImm(4 << align));
Inst.addOperand(MCOperand::createImm(4 << align));
return S;
}
@@ -2475,7 +2475,7 @@ static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
case ARM::VLD2b8wb_register:
case ARM::VLD2b16wb_register:
case ARM::VLD2b32wb_register:
Inst.addOperand(MCOperand::CreateImm(0));
Inst.addOperand(MCOperand::createImm(0));
break;
case ARM::VLD3d8_UPD:
case ARM::VLD3d16_UPD:
@@ -2510,7 +2510,7 @@ static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
//
// The fixed offset encodes as Rm == 0xd, so we check for that.
if (Rm == 0xd) {
Inst.addOperand(MCOperand::CreateReg(0));
Inst.addOperand(MCOperand::createReg(0));
break;
}
// Fall through to handle the register offset variant.
@@ -2676,7 +2676,7 @@ static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
case ARM::VST2b32wb_register:
if (Rm == 0xF)
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(0));
Inst.addOperand(MCOperand::createImm(0));
break;
case ARM::VST3d8_UPD:
case ARM::VST3d16_UPD:
@@ -2705,7 +2705,7 @@ static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
switch (Inst.getOpcode()) {
default:
if (Rm == 0xD)
Inst.addOperand(MCOperand::CreateReg(0));
Inst.addOperand(MCOperand::createReg(0));
else if (Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
@@ -2917,7 +2917,7 @@ static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(align));
Inst.addOperand(MCOperand::createImm(align));
// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
// variant encodes Rm == 0xf. Anything else is a register offset post-
@@ -2963,11 +2963,11 @@ static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
}
if (Rm != 0xF)
Inst.addOperand(MCOperand::CreateImm(0));
Inst.addOperand(MCOperand::createImm(0));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(align));
Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xD && Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
@@ -3000,10 +3000,10 @@ static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(0));
Inst.addOperand(MCOperand::createImm(0));
if (Rm == 0xD)
Inst.addOperand(MCOperand::CreateReg(0));
Inst.addOperand(MCOperand::createReg(0));
else if (Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
@@ -3052,10 +3052,10 @@ static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(align));
Inst.addOperand(MCOperand::createImm(align));
if (Rm == 0xD)
Inst.addOperand(MCOperand::CreateReg(0));
Inst.addOperand(MCOperand::createReg(0));
else if (Rm != 0xF) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
@@ -3086,7 +3086,7 @@ DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
return MCDisassembler::Fail;
}
Inst.addOperand(MCOperand::CreateImm(imm));
Inst.addOperand(MCOperand::createImm(imm));
switch (Inst.getOpcode()) {
case ARM::VORRiv4i16:
@@ -3124,32 +3124,32 @@ static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(8 << size));
Inst.addOperand(MCOperand::createImm(8 << size));
return S;
}
static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
Inst.addOperand(MCOperand::CreateImm(8 - Val));
Inst.addOperand(MCOperand::createImm(8 - Val));
return MCDisassembler::Success;
}
static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
Inst.addOperand(MCOperand::CreateImm(16 - Val));
Inst.addOperand(MCOperand::createImm(16 - Val));
return MCDisassembler::Success;
}
static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
Inst.addOperand(MCOperand::CreateImm(32 - Val));
Inst.addOperand(MCOperand::createImm(32 - Val));
return MCDisassembler::Success;
}
static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
Inst.addOperand(MCOperand::CreateImm(64 - Val));
Inst.addOperand(MCOperand::createImm(64 - Val));
return MCDisassembler::Success;
}
@@ -3205,11 +3205,11 @@ static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
case ARM::tADR:
break; // tADR does not explicitly represent the PC as an operand.
case ARM::tADDrSPi:
Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Inst.addOperand(MCOperand::createReg(ARM::SP));
break;
}
Inst.addOperand(MCOperand::CreateImm(imm));
Inst.addOperand(MCOperand::createImm(imm));
return S;
}
@@ -3217,7 +3217,7 @@ static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
true, 2, Inst, Decoder))
Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
return MCDisassembler::Success;
}
@@ -3225,7 +3225,7 @@ static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
true, 4, Inst, Decoder))
Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
return MCDisassembler::Success;
}
@@ -3233,7 +3233,7 @@ static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
true, 2, Inst, Decoder))
Inst.addOperand(MCOperand::CreateImm(Val << 1));
Inst.addOperand(MCOperand::createImm(Val << 1));
return MCDisassembler::Success;
}
@@ -3261,7 +3261,7 @@ static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(imm));
Inst.addOperand(MCOperand::createImm(imm));
return S;
}
@@ -3270,7 +3270,7 @@ static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
unsigned imm = Val << 2;
Inst.addOperand(MCOperand::CreateImm(imm));
Inst.addOperand(MCOperand::createImm(imm));
tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
return MCDisassembler::Success;
@@ -3278,8 +3278,8 @@ static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Inst.addOperand(MCOperand::CreateImm(Val));
Inst.addOperand(MCOperand::createReg(ARM::SP));
Inst.addOperand(MCOperand::createImm(Val));
return MCDisassembler::Success;
}
@@ -3307,7 +3307,7 @@ static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
return MCDisassembler::Fail;
if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(imm));
Inst.addOperand(MCOperand::createImm(imm));
return S;
}
@@ -3641,7 +3641,7 @@ static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
else
imm = -imm;
}
Inst.addOperand(MCOperand::CreateImm(imm));
Inst.addOperand(MCOperand::createImm(imm));
return S;
}
@@ -3649,12 +3649,12 @@ static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
if (Val == 0)
Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
Inst.addOperand(MCOperand::createImm(INT32_MIN));
else {
int imm = Val & 0xFF;
if (!(Val & 0x100)) imm *= -1;
Inst.addOperand(MCOperand::CreateImm(imm * 4));
Inst.addOperand(MCOperand::createImm(imm * 4));
}
return MCDisassembler::Success;
@@ -3685,7 +3685,7 @@ static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(imm));
Inst.addOperand(MCOperand::createImm(imm));
return S;
}
@@ -3697,7 +3697,7 @@ static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
imm = INT32_MIN;
else if (!(Val & 0x100))
imm *= -1;
Inst.addOperand(MCOperand::CreateImm(imm));
Inst.addOperand(MCOperand::createImm(imm));
return MCDisassembler::Success;
}
@@ -3830,7 +3830,7 @@ static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(imm));
Inst.addOperand(MCOperand::createImm(imm));
return S;
}
@@ -3840,9 +3840,9 @@ static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
uint64_t Address, const void *Decoder) {
unsigned imm = fieldFromInstruction(Insn, 0, 7);
Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Inst.addOperand(MCOperand::CreateImm(imm));
Inst.addOperand(MCOperand::createReg(ARM::SP));
Inst.addOperand(MCOperand::createReg(ARM::SP));
Inst.addOperand(MCOperand::createImm(imm));
return MCDisassembler::Success;
}
@@ -3857,14 +3857,14 @@ static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Inst.addOperand(MCOperand::createReg(ARM::SP));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
return MCDisassembler::Fail;
} else if (Inst.getOpcode() == ARM::tADDspr) {
unsigned Rm = fieldFromInstruction(Insn, 3, 4);
Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Inst.addOperand(MCOperand::createReg(ARM::SP));
Inst.addOperand(MCOperand::createReg(ARM::SP));
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
}
@@ -3877,8 +3877,8 @@ static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
unsigned flags = fieldFromInstruction(Insn, 0, 3);
Inst.addOperand(MCOperand::CreateImm(imod));
Inst.addOperand(MCOperand::CreateImm(flags));
Inst.addOperand(MCOperand::createImm(imod));
Inst.addOperand(MCOperand::createImm(flags));
return MCDisassembler::Success;
}
@@ -3891,7 +3891,7 @@ static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(add));
Inst.addOperand(MCOperand::createImm(add));
return S;
}
@@ -3916,7 +3916,7 @@ static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
if (!tryAddingSymbolicOperand(Address,
(Address & ~2u) + imm32 + 4,
true, 4, Inst, Decoder))
Inst.addOperand(MCOperand::CreateImm(imm32));
Inst.addOperand(MCOperand::createImm(imm32));
return MCDisassembler::Success;
}
@@ -3930,7 +3930,7 @@ static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(Val));
Inst.addOperand(MCOperand::createImm(Val));
return MCDisassembler::Success;
}
@@ -4001,16 +4001,16 @@ static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
unsigned imm = fieldFromInstruction(Val, 0, 8);
switch (byte) {
case 0:
Inst.addOperand(MCOperand::CreateImm(imm));
Inst.addOperand(MCOperand::createImm(imm));
break;
case 1:
Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm));
Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
break;
case 2:
Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8)));
Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
break;
case 3:
Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) |
Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
(imm << 8) | imm));
break;
}
@@ -4018,7 +4018,7 @@ static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
unsigned rot = fieldFromInstruction(Val, 7, 5);
unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
Inst.addOperand(MCOperand::CreateImm(imm));
Inst.addOperand(MCOperand::createImm(imm));
}
return MCDisassembler::Success;
@@ -4029,7 +4029,7 @@ DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder){
if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
true, 2, Inst, Decoder))
Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
return MCDisassembler::Success;
}
@@ -4052,7 +4052,7 @@ static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
true, 4, Inst, Decoder))
Inst.addOperand(MCOperand::CreateImm(imm32));
Inst.addOperand(MCOperand::createImm(imm32));
return MCDisassembler::Success;
}
@@ -4061,7 +4061,7 @@ static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
if (Val & ~0xf)
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(Val));
Inst.addOperand(MCOperand::createImm(Val));
return MCDisassembler::Success;
}
@@ -4070,7 +4070,7 @@ static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
if (Val & ~0xf)
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(Val));
Inst.addOperand(MCOperand::createImm(Val));
return MCDisassembler::Success;
}
@@ -4132,7 +4132,7 @@ static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
if (Val == 0)
return MCDisassembler::Fail;
}
Inst.addOperand(MCOperand::CreateImm(Val));
Inst.addOperand(MCOperand::createImm(Val));
return S;
}
@@ -4155,7 +4155,7 @@ static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
return MCDisassembler::SoftFail;
}
Inst.addOperand(MCOperand::CreateImm(Val));
Inst.addOperand(MCOperand::createImm(Val));
return MCDisassembler::Success;
}
@@ -4359,18 +4359,18 @@ static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(align));
Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
Inst.addOperand(MCOperand::CreateReg(0));
Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(index));
Inst.addOperand(MCOperand::createImm(index));
return S;
}
@@ -4424,18 +4424,18 @@ static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(align));
Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
Inst.addOperand(MCOperand::CreateReg(0));
Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(index));
Inst.addOperand(MCOperand::createImm(index));
return S;
}
@@ -4490,20 +4490,20 @@ static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(align));
Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
Inst.addOperand(MCOperand::CreateReg(0));
Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(index));
Inst.addOperand(MCOperand::createImm(index));
return S;
}
@@ -4553,20 +4553,20 @@ static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(align));
Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
Inst.addOperand(MCOperand::CreateReg(0));
Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(index));
Inst.addOperand(MCOperand::createImm(index));
return S;
}
@@ -4622,13 +4622,13 @@ static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(align));
Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
Inst.addOperand(MCOperand::CreateReg(0));
Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
@@ -4637,7 +4637,7 @@ static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(index));
Inst.addOperand(MCOperand::createImm(index));
return S;
}
@@ -4685,13 +4685,13 @@ static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(align));
Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
Inst.addOperand(MCOperand::CreateReg(0));
Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
@@ -4700,7 +4700,7 @@ static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(index));
Inst.addOperand(MCOperand::createImm(index));
return S;
}
@@ -4765,13 +4765,13 @@ static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(align));
Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
Inst.addOperand(MCOperand::CreateReg(0));
Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
@@ -4782,7 +4782,7 @@ static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(index));
Inst.addOperand(MCOperand::createImm(index));
return S;
}
@@ -4837,13 +4837,13 @@ static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
}
if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(align));
Inst.addOperand(MCOperand::createImm(align));
if (Rm != 0xF) {
if (Rm != 0xD) {
if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
return MCDisassembler::Fail;
} else
Inst.addOperand(MCOperand::CreateReg(0));
Inst.addOperand(MCOperand::createReg(0));
}
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
@@ -4854,7 +4854,7 @@ static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(index));
Inst.addOperand(MCOperand::createImm(index));
return S;
}
@@ -4925,8 +4925,8 @@ static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
if (mask == 0x0)
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(pred));
Inst.addOperand(MCOperand::CreateImm(mask));
Inst.addOperand(MCOperand::createImm(pred));
Inst.addOperand(MCOperand::createImm(mask));
return S;
}
@@ -5012,7 +5012,7 @@ static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
Val |= fieldFromInstruction(Insn, 12, 3) << 8;
Val |= fieldFromInstruction(Insn, 26, 1) << 11;
Val |= sign1 << 12;
Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
Inst.addOperand(MCOperand::createImm(SignExtend32<13>(Val)));
return MCDisassembler::Success;
}
@@ -5024,7 +5024,7 @@ static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
// Shift of "asr #32" is not allowed in Thumb2 mode.
if (Val == 0x20) S = MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(Val));
Inst.addOperand(MCOperand::createImm(Val));
return S;
}
@@ -5080,7 +5080,7 @@ static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
return MCDisassembler::Fail;
if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(64 - imm));
Inst.addOperand(MCOperand::createImm(64 - imm));
return S;
}
@@ -5110,7 +5110,7 @@ static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
return MCDisassembler::Fail;
if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(64 - imm));
Inst.addOperand(MCOperand::createImm(64 - imm));
return S;
}
@@ -5159,13 +5159,13 @@ static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
if (Rt == Rt2)
S = MCDisassembler::SoftFail;
Inst.addOperand(MCOperand::CreateImm(cop));
Inst.addOperand(MCOperand::CreateImm(opc1));
Inst.addOperand(MCOperand::createImm(cop));
Inst.addOperand(MCOperand::createImm(opc1));
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
return MCDisassembler::Fail;
if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(CRm));
Inst.addOperand(MCOperand::createImm(CRm));
return S;
}