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MC: Modernize MCOperand API naming. NFC.

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MCOperand::Create*() methods renamed to MCOperand::create*().

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237275 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2015-05-13 18:37:00 +00:00
parent 428e9d7608
commit db703aaedd
55 changed files with 1190 additions and 1191 deletions
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18
lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
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@@ -204,7 +204,7 @@ static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
if (RegNo > 11)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, XCore::GRRegsRegClassID, RegNo);
Inst.addOperand(MCOperand::CreateReg(Reg));
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -216,7 +216,7 @@ static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
if (RegNo > 15)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, XCore::RRegsRegClassID, RegNo);
Inst.addOperand(MCOperand::CreateReg(Reg));
Inst.addOperand(MCOperand::createReg(Reg));
return MCDisassembler::Success;
}
@@ -227,13 +227,13 @@ static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
static unsigned Values[] = {
32 /*bpw*/, 1, 2, 3, 4, 5, 6, 7, 8, 16, 24, 32
};
Inst.addOperand(MCOperand::CreateImm(Values[Val]));
Inst.addOperand(MCOperand::createImm(Values[Val]));
return MCDisassembler::Success;
}
static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
uint64_t Address, const void *Decoder) {
Inst.addOperand(MCOperand::CreateImm(-(int64_t)Val));
Inst.addOperand(MCOperand::createImm(-(int64_t)Val));
return MCDisassembler::Success;
}
@@ -362,7 +362,7 @@ Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
if (S != MCDisassembler::Success)
return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
Inst.addOperand(MCOperand::CreateImm(Op1));
Inst.addOperand(MCOperand::createImm(Op1));
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
return S;
}
@@ -403,7 +403,7 @@ DecodeRUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
Inst.addOperand(MCOperand::CreateImm(Op2));
Inst.addOperand(MCOperand::createImm(Op2));
return S;
}
@@ -552,7 +552,7 @@ Decode3RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
unsigned Op1, Op2, Op3;
DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3);
if (S == MCDisassembler::Success) {
Inst.addOperand(MCOperand::CreateImm(Op1));
Inst.addOperand(MCOperand::createImm(Op1));
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder);
}
@@ -567,7 +567,7 @@ Decode2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
Inst.addOperand(MCOperand::CreateImm(Op3));
Inst.addOperand(MCOperand::createImm(Op3));
}
return S;
}
@@ -623,7 +623,7 @@ DecodeL2RUSInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
if (S == MCDisassembler::Success) {
DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder);
DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
Inst.addOperand(MCOperand::CreateImm(Op3));
Inst.addOperand(MCOperand::createImm(Op3));
}
return S;
}