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The return value of this call is not used, so no point

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in assigning it to a variable (gcc-4.6 warning).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117024 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duncan Sands
2010-10-21 16:06:28 +00:00
parent 2b55f56df8
commit dbbd99faf1
1 changed files with 7 additions and 8 deletions
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15
lib/Target/ARM/ARMExpandPseudoInsts.cpp
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@@ -628,14 +628,13 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
case ARM::MOVsrl_flag: case ARM::MOVsrl_flag:
case ARM::MOVsra_flag: { case ARM::MOVsra_flag: {
// These are just fancy MOVs insructions. // These are just fancy MOVs insructions.
MachineInstrBuilder MIB = AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs),
AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs), MI.getOperand(0).getReg())
MI.getOperand(0).getReg()) .addOperand(MI.getOperand(1))
.addOperand(MI.getOperand(1)) .addReg(0)
.addReg(0) .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr
.addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr : ARM_AM::asr), 1)))
: ARM_AM::asr), 1))) .addReg(ARM::CPSR, RegState::Define);
.addReg(ARM::CPSR, RegState::Define);
MI.eraseFromParent(); MI.eraseFromParent();
break; break;
} }