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[SystemZ] Rename PSW to CC

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Addresses a review comment from Ulrich Weigand.  No functional change intended.

I'm not sure whether the old TODO that this patch touches still holds,
but that's something we'd get to when adding a targetted scheduling
description.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182474 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Sandiford 2013-05-22 13:38:45 +00:00
parent d34c40514e
commit dbd8eb26ce
7 changed files with 37 additions and 43 deletions
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6
lib/Target/SystemZ/README.txt
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@ -60,12 +60,6 @@ We don't use the combined COMPARE AND BRANCH instructions.
--
We should probably model just CC, not the PSW as a whole. Strictly
speaking, every instruction changes the PSW since the PSW contains the
current instruction address.
--
We don't use the condition code results of anything except comparisons.
Implementing this may need something more finely grained than the z_cmp

2
lib/Target/SystemZ/SystemZFrameLowering.cpp
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@ -283,7 +283,7 @@ static void emitIncrement(MachineBasicBlock &MBB,
}
MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII->get(Opcode), Reg)
.addReg(Reg).addImm(ThisVal);
// The PSW implicit def is dead.
// The CC implicit def is dead.
MI->getOperand(3).setIsDead();
NumBytes -= ThisVal;
}

2
lib/Target/SystemZ/SystemZISelLowering.cpp
View File

@ -67,7 +67,7 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm)
// TODO: It may be better to default to latency-oriented scheduling, however
// LLVM's current latency-oriented scheduler can't handle physreg definitions
// such as SystemZ has with PSW, so set this to the register-pressure
// such as SystemZ has with CC, so set this to the register-pressure
// scheduler, because it can.
setSchedulingPreference(Sched::RegPressure);

18
lib/Target/SystemZ/SystemZInstrFP.td
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@ -129,7 +129,7 @@ def LXEB : UnaryRXE<"lxeb", 0xED06, extloadf32, FP128>;
def LXDB : UnaryRXE<"lxdb", 0xED05, extloadf64, FP128>;
// Convert a signed integer register value to a floating-point one.
let Defs = [PSW] in {
let Defs = [CC] in {
def CEFBR : UnaryRRE<"cefbr", 0xB394, sint_to_fp, FP32, GR32>;
def CDFBR : UnaryRRE<"cdfbr", 0xB395, sint_to_fp, FP64, GR32>;
def CXFBR : UnaryRRE<"cxfbr", 0xB396, sint_to_fp, FP128, GR32>;
@ -141,7 +141,7 @@ let Defs = [PSW] in {
// Convert a floating-point register value to a signed integer value,
// with the second operand (modifier M3) specifying the rounding mode.
let Defs = [PSW] in {
let Defs = [CC] in {
def CFEBR : UnaryRRF<"cfebr", 0xB398, GR32, FP32>;
def CFDBR : UnaryRRF<"cfdbr", 0xB399, GR32, FP64>;
def CFXBR : UnaryRRF<"cfxbr", 0xB39A, GR32, FP128>;
@ -165,21 +165,21 @@ def : Pat<(i64 (fp_to_sint FP128:$src)), (CGXBR 5, FP128:$src)>;
//===----------------------------------------------------------------------===//
// Negation (Load Complement).
let Defs = [PSW] in {
let Defs = [CC] in {
def LCEBR : UnaryRRE<"lcebr", 0xB303, fneg, FP32, FP32>;
def LCDBR : UnaryRRE<"lcdbr", 0xB313, fneg, FP64, FP64>;
def LCXBR : UnaryRRE<"lcxbr", 0xB343, fneg, FP128, FP128>;
}
// Absolute value (Load Positive).
let Defs = [PSW] in {
let Defs = [CC] in {
def LPEBR : UnaryRRE<"lpebr", 0xB300, fabs, FP32, FP32>;
def LPDBR : UnaryRRE<"lpdbr", 0xB310, fabs, FP64, FP64>;
def LPXBR : UnaryRRE<"lpxbr", 0xB340, fabs, FP128, FP128>;
}
// Negative absolute value (Load Negative).
let Defs = [PSW] in {
let Defs = [CC] in {
def LNEBR : UnaryRRE<"lnebr", 0xB301, fnabs, FP32, FP32>;
def LNDBR : UnaryRRE<"lndbr", 0xB311, fnabs, FP64, FP64>;
def LNXBR : UnaryRRE<"lnxbr", 0xB341, fnabs, FP128, FP128>;
@ -199,7 +199,7 @@ def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<fsqrt>, FP64>;
// These forms always check for inexact conditions. z196 added versions
// that allow this to suppressed (as for fnearbyint), but we don't yet
// support -march=z196.
let Defs = [PSW] in {
let Defs = [CC] in {
def FIEBR : UnaryRRF<"fiebr", 0xB357, FP32, FP32>;
def FIDBR : UnaryRRF<"fidbr", 0xB35F, FP64, FP64>;
def FIXBR : UnaryRRF<"fixbr", 0xB347, FP128, FP128>;
@ -216,7 +216,7 @@ def : Pat<(frint FP128:$src), (FIXBR 0, FP128:$src)>;
//===----------------------------------------------------------------------===//
// Addition.
let Defs = [PSW] in {
let Defs = [CC] in {
let isCommutable = 1 in {
def AEBR : BinaryRRE<"aebr", 0xB30A, fadd, FP32, FP32>;
def ADBR : BinaryRRE<"adbr", 0xB31A, fadd, FP64, FP64>;
@ -227,7 +227,7 @@ let Defs = [PSW] in {
}
// Subtraction.
let Defs = [PSW] in {
let Defs = [CC] in {
def SEBR : BinaryRRE<"sebr", 0xB30B, fsub, FP32, FP32>;
def SDBR : BinaryRRE<"sdbr", 0xB31B, fsub, FP64, FP64>;
def SXBR : BinaryRRE<"sxbr", 0xB34B, fsub, FP128, FP128>;
@ -297,7 +297,7 @@ def DDB : BinaryRXE<"ddb", 0xED1D, fdiv, FP64, load>;
// Comparisons
//===----------------------------------------------------------------------===//
let Defs = [PSW] in {
let Defs = [CC] in {
def CEBR : CompareRRE<"cebr", 0xB309, z_cmp, FP32, FP32>;
def CDBR : CompareRRE<"cdbr", 0xB319, z_cmp, FP64, FP64>;
def CXBR : CompareRRE<"cxbr", 0xB349, z_cmp, FP128, FP128>;

12
lib/Target/SystemZ/SystemZInstrFormats.td
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@ -913,10 +913,10 @@ class SelectWrapper<RegisterOperand cls>
[(set cls:$dst, (z_select_ccmask cls:$src1, cls:$src2, imm:$cc))]> {
let usesCustomInserter = 1;
// Although the instructions used by these nodes do not in themselves
// change the PSW, the insertion requires new blocks, and the PSW cannot
// be live across them.
let Defs = [PSW];
let Uses = [PSW];
// change CC, the insertion requires new blocks, and CC cannot be live
// across them.
let Defs = [CC];
let Uses = [CC];
}
// OPERATOR is ATOMIC_SWAP or an ATOMIC_LOAD_* operation. PAT and OPERAND
@ -925,7 +925,7 @@ class AtomicLoadBinary<SDPatternOperator operator, RegisterOperand cls,
dag pat, DAGOperand operand>
: Pseudo<(outs cls:$dst), (ins bdaddr20only:$ptr, operand:$src2),
[(set cls:$dst, (operator bdaddr20only:$ptr, pat))]> {
let Defs = [PSW];
let Defs = [CC];
let Has20BitOffset = 1;
let mayLoad = 1;
let mayStore = 1;
@ -951,7 +951,7 @@ class AtomicLoadWBinary<SDPatternOperator operator, dag pat,
ADDR32:$negbitshift, uimm32:$bitsize),
[(set GR32:$dst, (operator bdaddr20only:$ptr, pat, ADDR32:$bitshift,
ADDR32:$negbitshift, uimm32:$bitsize))]> {
let Defs = [PSW];
let Defs = [CC];
let Has20BitOffset = 1;
let mayLoad = 1;
let mayStore = 1;

36
lib/Target/SystemZ/SystemZInstrInfo.td
View File

@ -59,7 +59,7 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in {
// the first operand. It seems friendlier to use mnemonic forms like
// JE and JLH when writing out the assembly though.
multiclass CondBranches<Operand imm, string short, string long> {
let isBranch = 1, isTerminator = 1, Uses = [PSW] in {
let isBranch = 1, isTerminator = 1, Uses = [CC] in {
def "" : InstRI<0xA74, (outs), (ins imm:$R1, brtarget16:$I2), short, []>;
def L : InstRIL<0xC04, (outs), (ins imm:$R1, brtarget32:$I2), long, []>;
}
@ -349,7 +349,7 @@ let neverHasSideEffects = 1 in {
// Negation
//===----------------------------------------------------------------------===//
let Defs = [PSW] in {
let Defs = [CC] in {
def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>;
def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>;
def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>;
@ -403,7 +403,7 @@ def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm),
//===----------------------------------------------------------------------===//
// Plain addition.
let Defs = [PSW] in {
let Defs = [CC] in {
// Addition of a register.
let isCommutable = 1 in {
def AR : BinaryRR <"ar", 0x1A, add, GR32, GR32>;
@ -432,7 +432,7 @@ let Defs = [PSW] in {
defm : SXB<add, GR64, AGFR>;
// Addition producing a carry.
let Defs = [PSW] in {
let Defs = [CC] in {
// Addition of a register.
let isCommutable = 1 in {
def ALR : BinaryRR <"alr", 0x1E, addc, GR32, GR32>;
@ -452,7 +452,7 @@ let Defs = [PSW] in {
defm : ZXB<addc, GR64, ALGFR>;
// Addition producing and using a carry.
let Defs = [PSW], Uses = [PSW] in {
let Defs = [CC], Uses = [CC] in {
// Addition of a register.
def ALCR : BinaryRRE<"alcr", 0xB998, adde, GR32, GR32>;
def ALCGR : BinaryRRE<"alcgr", 0xB988, adde, GR64, GR64>;
@ -468,7 +468,7 @@ let Defs = [PSW], Uses = [PSW] in {
// Plain substraction. Although immediate forms exist, we use the
// add-immediate instruction instead.
let Defs = [PSW] in {
let Defs = [CC] in {
// Subtraction of a register.
def SR : BinaryRR <"sr", 0x1B, sub, GR32, GR32>;
def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>;
@ -483,7 +483,7 @@ let Defs = [PSW] in {
defm : SXB<sub, GR64, SGFR>;
// Subtraction producing a carry.
let Defs = [PSW] in {
let Defs = [CC] in {
// Subtraction of a register.
def SLR : BinaryRR <"slr", 0x1F, subc, GR32, GR32>;
def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>;
@ -502,7 +502,7 @@ let Defs = [PSW] in {
defm : ZXB<subc, GR64, SLGFR>;
// Subtraction producing and using a carry.
let Defs = [PSW], Uses = [PSW] in {
let Defs = [CC], Uses = [CC] in {
// Subtraction of a register.
def SLBR : BinaryRRE<"slbr", 0xB999, sube, GR32, GR32>;
def SLGBR : BinaryRRE<"slbgr", 0xB989, sube, GR64, GR64>;
@ -516,7 +516,7 @@ let Defs = [PSW], Uses = [PSW] in {
// AND
//===----------------------------------------------------------------------===//
let Defs = [PSW] in {
let Defs = [CC] in {
// ANDs of a register.
let isCommutable = 1 in {
def NR : BinaryRR <"nr", 0x14, and, GR32, GR32>;
@ -553,7 +553,7 @@ defm : RMWIByte<and, bdaddr20pair, NIY>;
// OR
//===----------------------------------------------------------------------===//
let Defs = [PSW] in {
let Defs = [CC] in {
// ORs of a register.
let isCommutable = 1 in {
def OR : BinaryRR <"or", 0x16, or, GR32, GR32>;
@ -590,7 +590,7 @@ defm : RMWIByte<or, bdaddr20pair, OIY>;
// XOR
//===----------------------------------------------------------------------===//
let Defs = [PSW] in {
let Defs = [CC] in {
// XORs of a register.
let isCommutable = 1 in {
def XR : BinaryRR <"xr", 0x17, xor, GR32, GR32>;
@ -679,7 +679,7 @@ let neverHasSideEffects = 1 in {
}
// Arithmetic shift right.
let Defs = [PSW] in {
let Defs = [CC] in {
def SRA : ShiftRS <"sra", 0x8A, sra, GR32, shift12only>;
def SRAG : ShiftRSY<"srag", 0xEB0A, sra, GR64, shift20only>;
}
@ -693,7 +693,7 @@ let neverHasSideEffects = 1 in {
// Rotate second operand left and inserted selected bits into first operand.
// These can act like 32-bit operands provided that the constant start and
// end bits (operands 2 and 3) are in the range [32, 64)
let Defs = [PSW] in {
let Defs = [CC] in {
let isCodeGenOnly = 1 in
def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>;
def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>;
@ -704,7 +704,7 @@ let Defs = [PSW] in {
//===----------------------------------------------------------------------===//
// Signed comparisons.
let Defs = [PSW] in {
let Defs = [CC] in {
// Comparison with a register.
def CR : CompareRR <"cr", 0x19, z_cmp, GR32, GR32>;
def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>;
@ -738,7 +738,7 @@ let Defs = [PSW] in {
defm : SXB<z_cmp, GR64, CGFR>;
// Unsigned comparisons.
let Defs = [PSW] in {
let Defs = [CC] in {
// Comparison with a register.
def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>;
def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>;
@ -877,13 +877,13 @@ def ATOMIC_CMP_SWAPW
(z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
ADDR32:$bitshift, ADDR32:$negbitshift,
uimm32:$bitsize))]> {
let Defs = [PSW];
let Defs = [CC];
let mayLoad = 1;
let mayStore = 1;
let usesCustomInserter = 1;
}
let Defs = [PSW] in {
let Defs = [CC] in {
defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>;
def CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>;
}
@ -903,7 +903,7 @@ def EAR : InstRRE<0xB24F, (outs GR32:$R1), (ins access_reg:$R2),
// returns a pair of GR64s, the first giving the number of leading zeros
// and the second giving a copy of the source with the leftmost one bit
// cleared. We only use the first result here.
let Defs = [PSW] in {
let Defs = [CC] in {
def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>;
}
def : Pat<(ctlz GR64:$src),

4
lib/Target/SystemZ/SystemZRegisterInfo.td
View File

@ -146,5 +146,5 @@ defm FP128 : SystemZRegClass<"FP128", f128, 128, (add F0Q, F1Q, F4Q, F5Q,
// Other registers
//===----------------------------------------------------------------------===//
// Status register
def PSW : SystemZReg<"psw">;
// The 2-bit condition code field of the PSW.
def CC : SystemZReg<"cc">;