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Fix a few typos

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193723 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2013-10-30 23:43:29 +00:00
parent 4f17f88071
commit dbd936f6cc
1 changed files with 7 additions and 7 deletions
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14
lib/Target/R600/R600ISelLowering.cpp
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@ -1253,13 +1253,13 @@ SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
return DAG.getMergeValues(MergedValues, 2, DL);
}
// For most operations returning SDValue() will result int he node being
// expanded by the DAG Legalizer. This is not the case for ISD::LOAD, so
// we need to manually expand loads that may be legal in some address spaces
// and illegal in others. SEXT loads from CONSTANT_BUFFER_0 are supported
// for compute shaders, since the data is sign extended when it is uploaded
// to the buffer. Howerver SEXT loads from other addresspaces are not
// supported, so we need to expand them here.
// For most operations returning SDValue() will result in the node being
// expanded by the DAG Legalizer. This is not the case for ISD::LOAD, so we
// need to manually expand loads that may be legal in some address spaces and
// illegal in others. SEXT loads from CONSTANT_BUFFER_0 are supported for
// compute shaders, since the data is sign extended when it is uploaded to the
// buffer. However SEXT loads from other address spaces are not supported, so
// we need to expand them here.
if (LoadNode->getExtensionType() == ISD::SEXTLOAD) {
EVT MemVT = LoadNode->getMemoryVT();
assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8));