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Fix a few typos
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193723 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1253,13 +1253,13 @@ SDValue R600TargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const
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return DAG.getMergeValues(MergedValues, 2, DL);
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return DAG.getMergeValues(MergedValues, 2, DL);
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}
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}
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// For most operations returning SDValue() will result int he node being
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// For most operations returning SDValue() will result in the node being
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// expanded by the DAG Legalizer. This is not the case for ISD::LOAD, so
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// expanded by the DAG Legalizer. This is not the case for ISD::LOAD, so we
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// we need to manually expand loads that may be legal in some address spaces
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// need to manually expand loads that may be legal in some address spaces and
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// and illegal in others. SEXT loads from CONSTANT_BUFFER_0 are supported
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// illegal in others. SEXT loads from CONSTANT_BUFFER_0 are supported for
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// for compute shaders, since the data is sign extended when it is uploaded
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// compute shaders, since the data is sign extended when it is uploaded to the
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// to the buffer. Howerver SEXT loads from other addresspaces are not
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// buffer. However SEXT loads from other address spaces are not supported, so
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// supported, so we need to expand them here.
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// we need to expand them here.
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if (LoadNode->getExtensionType() == ISD::SEXTLOAD) {
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if (LoadNode->getExtensionType() == ISD::SEXTLOAD) {
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EVT MemVT = LoadNode->getMemoryVT();
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EVT MemVT = LoadNode->getMemoryVT();
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assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8));
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assert(!MemVT.isVector() && (MemVT == MVT::i16 || MemVT == MVT::i8));
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