Move some sub-register index calculations to CodeGenRegisters.cpp

Create a new CodeGenRegBank class that will eventually hold all the code
that computes the register structure from Records.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132849 91177308-0d34-0410-b5e6-96231b3b80d8

utils/TableGen/CodeGenRegisters.cpp

@@ -99,3 +99,30 @@ const std::string &CodeGenRegisterClass::getName() const {
   return TheDef->getName();
 }
 
+//===----------------------------------------------------------------------===//
+//                               CodeGenRegBank
+//===----------------------------------------------------------------------===//
+
+CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) : Records(Records) {
+  // Read in the user-defined (named) sub-register indices. More indices will
+  // be synthesized.
+  SubRegIndices = Records.getAllDerivedDefinitions("SubRegIndex");
+  std::sort(SubRegIndices.begin(), SubRegIndices.end(), LessRecord());
+  NumNamedIndices = SubRegIndices.size();
+}
+
+Record *CodeGenRegBank::getCompositeSubRegIndex(Record *A, Record *B) {
+  std::string Name = A->getName() + "_then_" + B->getName();
+  Record *R = new Record(Name, SMLoc(), Records);
+  Records.addDef(R);
+  SubRegIndices.push_back(R);
+  return R;
+}
+
+unsigned CodeGenRegBank::getSubRegIndexNo(Record *idx) {
+  std::vector<Record*>::const_iterator i =
+    std::find(SubRegIndices.begin(), SubRegIndices.end(), idx);
+  assert(i != SubRegIndices.end() && "Not a SubRegIndex");
+  return (i - SubRegIndices.begin()) + 1;
+}
+

utils/TableGen/CodeGenRegisters.h

@@ -24,6 +24,7 @@
 
 namespace llvm {
   class Record;
+  class RecordKeeper;
 
   /// CodeGenRegister - Represents a register definition.
   struct CodeGenRegister {
@@ -98,6 +99,32 @@ namespace llvm {
 
     CodeGenRegisterClass(Record *R);
   };
+
+  // CodeGenRegBank - Represent a target's registers and the relations between
+  // them.
+  class CodeGenRegBank {
+    RecordKeeper &Records;
+
+    // Sub-register indices. The first NumNamedIndices are defined by the user
+    // in the .td files. The rest are synthesized such that all sub-registers
+    // have a unique name.
+    std::vector<Record*> SubRegIndices;
+
+    unsigned NumNamedIndices;
+
+  public:
+    CodeGenRegBank(RecordKeeper&);
+
+    const std::vector<Record*> &getSubRegIndices() { return SubRegIndices; }
+
+    unsigned getNumNamedIndices() { return NumNamedIndices; }
+
+    // Map a SubRegIndex Record to its enum value.
+    unsigned getSubRegIndexNo(Record *idx);
+
+    // Create a new sub-register index representing the A+B composition.
+    Record *getCompositeSubRegIndex(Record *A, Record *B);
+  };
 }
 
 #endif

utils/TableGen/CodeGenTarget.cpp

@@ -108,7 +108,8 @@ std::string llvm::getQualifiedName(const Record *R) {
 
 /// getTarget - Return the current instance of the Target class.
 ///
-CodeGenTarget::CodeGenTarget(RecordKeeper &records) : Records(records) {
+CodeGenTarget::CodeGenTarget(RecordKeeper &records)
+  : Records(records), RegBank(0) {
   std::vector<Record*> Targets = Records.getAllDerivedDefinitions("Target");
   if (Targets.size() == 0)
     throw std::string("ERROR: No 'Target' subclasses defined!");
@@ -156,6 +157,12 @@ Record *CodeGenTarget::getAsmWriter() const {
   return LI[AsmWriterNum];
 }
 
+CodeGenRegBank &CodeGenTarget::getRegBank() const {
+  if (!RegBank)
+    RegBank = new CodeGenRegBank(Records);
+  return *RegBank;
+}
+
 void CodeGenTarget::ReadRegisters() const {
   std::vector<Record*> Regs = Records.getAllDerivedDefinitions("Register");
   if (Regs.empty())
@@ -169,18 +176,6 @@ void CodeGenTarget::ReadRegisters() const {
     Registers[i].EnumValue = i + 1;
 }
 
-void CodeGenTarget::ReadSubRegIndices() const {
-  SubRegIndices = Records.getAllDerivedDefinitions("SubRegIndex");
-  std::sort(SubRegIndices.begin(), SubRegIndices.end(), LessRecord());
-}
-
-Record *CodeGenTarget::createSubRegIndex(const std::string &Name) {
-  Record *R = new Record(Name, SMLoc(), Records);
-  Records.addDef(R);
-  SubRegIndices.push_back(R);
-  return R;
-}
-
 void CodeGenTarget::ReadRegisterClasses() const {
   std::vector<Record*> RegClasses =
     Records.getAllDerivedDefinitions("RegisterClass");

utils/TableGen/CodeGenTarget.h

@@ -65,12 +65,11 @@ class CodeGenTarget {
   Record *TargetRec;
 
   mutable DenseMap<const Record*, CodeGenInstruction*> Instructions;
+  mutable CodeGenRegBank *RegBank;
   mutable std::vector<CodeGenRegister> Registers;
-  mutable std::vector<Record*> SubRegIndices;
   mutable std::vector<CodeGenRegisterClass> RegisterClasses;
   mutable std::vector<MVT::SimpleValueType> LegalValueTypes;
   void ReadRegisters() const;
-  void ReadSubRegIndices() const;
   void ReadRegisterClasses() const;
   void ReadInstructions() const;
   void ReadLegalValueTypes() const;
@@ -98,6 +97,9 @@ public:
   ///
   Record *getAsmWriter() const;
 
+  /// getRegBank - Return the register bank description.
+  CodeGenRegBank &getRegBank() const;
+
   const std::vector<CodeGenRegister> &getRegisters() const {
     if (Registers.empty()) ReadRegisters();
     return Registers;
@@ -107,23 +109,6 @@ public:
   /// return it.
   const CodeGenRegister *getRegisterByName(StringRef Name) const;
 
-  const std::vector<Record*> &getSubRegIndices() const {
-    if (SubRegIndices.empty()) ReadSubRegIndices();
-    return SubRegIndices;
-  }
-
-  // Map a SubRegIndex Record to its number.
-  unsigned getSubRegIndexNo(Record *idx) const {
-    if (SubRegIndices.empty()) ReadSubRegIndices();
-    std::vector<Record*>::const_iterator i =
-      std::find(SubRegIndices.begin(), SubRegIndices.end(), idx);
-    assert(i != SubRegIndices.end() && "Not a SubRegIndex");
-    return (i - SubRegIndices.begin()) + 1;
-  }
-
-  // Create a new SubRegIndex with the given name.
-  Record *createSubRegIndex(const std::string &Name);
-
   const std::vector<CodeGenRegisterClass> &getRegisterClasses() const {
     if (RegisterClasses.empty()) ReadRegisterClasses();
     return RegisterClasses;

utils/TableGen/RegisterInfoEmitter.cpp

@@ -26,6 +26,7 @@ using namespace llvm;
 // runEnums - Print out enum values for all of the registers.
 void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
   CodeGenTarget Target(Records);
+  CodeGenRegBank &Bank = Target.getRegBank();
   const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
 
   std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
@@ -47,14 +48,14 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
   if (!Namespace.empty())
     OS << "}\n";
 
-  const std::vector<Record*> SubRegIndices = Target.getSubRegIndices();
+  const std::vector<Record*> &SubRegIndices = Bank.getSubRegIndices();
   if (!SubRegIndices.empty()) {
     OS << "\n// Subregister indices\n";
     Namespace = SubRegIndices[0]->getValueAsString("Namespace");
     if (!Namespace.empty())
       OS << "namespace " << Namespace << " {\n";
     OS << "enum {\n  NoSubRegister,\n";
-    for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
+    for (unsigned i = 0, e = Bank.getNumNamedIndices(); i != e; ++i)
       OS << "  " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
     OS << "  NUM_TARGET_NAMED_SUBREGS = " << SubRegIndices.size()+1 << "\n";
     OS << "};\n";
@@ -257,8 +258,8 @@ RegisterMaps::SubRegMap &RegisterMaps::inferSubRegIndices(Record *Reg,
        ++I) {
     Record *&Comp = Composite[I->second];
     if (!Comp)
-      Comp = Target.createSubRegIndex(I->second.first->getName() + "_then_" +
-                                      I->second.second->getName());
+      Comp = Target.getRegBank().getCompositeSubRegIndex(I->second.first,
+                                                         I->second.second);
     SRM[Comp] = I->first;
   }
 
@@ -338,6 +339,7 @@ public:
 //
 void RegisterInfoEmitter::run(raw_ostream &OS) {
   CodeGenTarget Target(Records);
+  CodeGenRegBank &RegBank = Target.getRegBank();
   EmitSourceFileHeader("Register Information Source Fragment", OS);
 
   OS << "namespace llvm {\n\n";
@@ -404,7 +406,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
     std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
     OS << "\n";
 
-    unsigned NumSubRegIndices = Target.getSubRegIndices().size();
+    unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
 
     if (NumSubRegIndices) {
       // Emit the sub-register classes for each RegisterClass
@@ -415,7 +417,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
              i = RC.SubRegClasses.begin(),
              e = RC.SubRegClasses.end(); i != e; ++i) {
           // Build SRC array.
-          unsigned idx = Target.getSubRegIndexNo(i->first);
+          unsigned idx = RegBank.getSubRegIndexNo(i->first);
           SRC.at(idx-1) = i->second;
 
           // Find the register class number of i->second for SuperRegClassMap.
@@ -863,13 +865,13 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
 
   // Calculate the mapping of subregister+index pairs to physical registers.
   // This will also create further anonymous indexes.
-  unsigned NamedIndices = Target.getSubRegIndices().size();
+  unsigned NamedIndices = RegBank.getNumNamedIndices();
   RegisterMaps RegMaps;
   for (unsigned i = 0, e = Regs.size(); i != e; ++i)
     RegMaps.inferSubRegIndices(Regs[i].TheDef, Target);
 
   // Emit SubRegIndex names, skipping 0
-  const std::vector<Record*> SubRegIndices = Target.getSubRegIndices();
+  const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices();
   OS << "\n  const char *const SubRegIndexTable[] = { \"";
   for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
     OS << SubRegIndices[i]->getName();