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[mips] [IAS] Add support for BNE and BEQ with an immediate operand.

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Summary:
For some branches, GAS accepts an immediate instead of the 2nd register operand.
We only implement this for BNE and BEQ for now. Other branch instructions can be added later, if needed.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: seanbruno, emaste, llvm-commits

Differential Revision: http://reviews.llvm.org/D9666

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239396 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Toma Tabacu
2015-06-09 10:34:31 +00:00
parent 4b0e9f114c
commit dc2af2605f
6 changed files with 219 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

61
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@@ -208,6 +208,9 @@ class MipsAsmParser : public MCTargetAsmParser {
bool expandLoadStoreMultiple(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions);
bool expandBranchImm(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions);
void createNop(bool hasShortDelaySlot, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions);
@@ -1616,6 +1619,8 @@ bool MipsAsmParser::needsExpansion(MCInst &Inst) {
case Mips::SWM_MM:
case Mips::JalOneReg:
case Mips::JalTwoReg:
case Mips::BneImm:
case Mips::BeqImm:
return true;
default:
return false;
@@ -1642,6 +1647,9 @@ bool MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
case Mips::JalOneReg:
case Mips::JalTwoReg:
return expandJalWithRegs(Inst, IDLoc, Instructions);
case Mips::BneImm:
case Mips::BeqImm:
return expandBranchImm(Inst, IDLoc, Instructions);
}
}
@@ -2032,6 +2040,59 @@ bool MipsAsmParser::expandUncondBranchMMPseudo(
return false;
}
bool MipsAsmParser::expandBranchImm(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions) {
const MCOperand &DstRegOp = Inst.getOperand(0);
assert(DstRegOp.isReg() && "expected register operand kind");
const MCOperand &ImmOp = Inst.getOperand(1);
assert(ImmOp.isImm() && "expected immediate operand kind");
const MCOperand &MemOffsetOp = Inst.getOperand(2);
assert(MemOffsetOp.isImm() && "expected immediate operand kind");
unsigned OpCode = 0;
switch(Inst.getOpcode()) {
case Mips::BneImm:
OpCode = Mips::BNE;
break;
case Mips::BeqImm:
OpCode = Mips::BEQ;
break;
default:
llvm_unreachable("Unknown immediate branch pseudo-instruction.");
break;
}
int64_t ImmValue = ImmOp.getImm();
if (ImmValue == 0) {
MCInst BranchInst;
BranchInst.setOpcode(OpCode);
BranchInst.addOperand(DstRegOp);
BranchInst.addOperand(MCOperand::createReg(Mips::ZERO));
BranchInst.addOperand(MemOffsetOp);
Instructions.push_back(BranchInst);
} else {
warnIfNoMacro(IDLoc);
unsigned ATReg = getATReg(IDLoc);
if (!ATReg)
return true;
if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, !isGP64bit(), IDLoc,
Instructions))
return true;
MCInst BranchInst;
BranchInst.setOpcode(OpCode);
BranchInst.addOperand(DstRegOp);
BranchInst.addOperand(MCOperand::createReg(ATReg));
BranchInst.addOperand(MemOffsetOp);
Instructions.push_back(BranchInst);
}
return false;
}
void MipsAsmParser::expandMemInst(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions,
bool isLoad, bool isImmOpnd) {

2
lib/Target/Mips/Mips64InstrInfo.td
View File

@@ -27,8 +27,6 @@ def uimm16_64 : Operand<i64> {
// Signed Operand
def simm10_64 : Operand<i64>;
def imm64: Operand<i64>;
// Transformation Function - get Imm - 32.
def Subtract32 : SDNodeXForm<imm, [{
return getImm(N, (unsigned)N->getZExtValue() - 32);