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https://github.com/c64scene-ar/llvm-6502.git
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Whitespace cleanup in ARM fast isel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116197 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher
parent
6a880d6ba8
commit
dccd2c3c43
@ -149,7 +149,7 @@ class ARMFastISel : public FastISel {
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// Call handling routines.
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private:
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CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool Return);
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bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
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bool ProcessCallArgs(SmallVectorImpl<Value*> &Args,
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SmallVectorImpl<unsigned> &ArgRegs,
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SmallVectorImpl<EVT> &ArgVTs,
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SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
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@ -365,7 +365,7 @@ unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
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// checks from the various callers.
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unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
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if (VT.getSimpleVT().SimpleTy == MVT::f64) return 0;
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unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(ARM::VMOVRS), MoveReg)
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@ -375,7 +375,7 @@ unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
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unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) {
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if (VT.getSimpleVT().SimpleTy == MVT::i64) return 0;
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unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(ARM::VMOVSR), MoveReg)
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@ -400,10 +400,10 @@ unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
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.addFPImm(CFP));
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return DestReg;
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}
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// Require VFP2 for loading fp constants.
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if (!Subtarget->hasVFP2()) return false;
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// MachineConstantPool wants an explicit alignment.
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unsigned Align = TD.getPrefTypeAlignment(CFP->getType());
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if (Align == 0) {
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@ -413,7 +413,7 @@ unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
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unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
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unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
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unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS;
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// The extra reg is for addrmode5.
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
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DestReg)
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@ -423,10 +423,10 @@ unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
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}
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unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
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// For now 32-bit only.
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if (VT.getSimpleVT().SimpleTy != MVT::i32) return false;
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// MachineConstantPool wants an explicit alignment.
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unsigned Align = TD.getPrefTypeAlignment(C->getType());
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if (Align == 0) {
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@ -435,7 +435,7 @@ unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
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}
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unsigned Idx = MCP.getConstantPoolIndex(C, Align);
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unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
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if (isThumb)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(ARM::t2LDRpci), DestReg)
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@ -453,29 +453,29 @@ unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
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unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
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// For now 32-bit only.
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if (VT.getSimpleVT().SimpleTy != MVT::i32) return 0;
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Reloc::Model RelocM = TM.getRelocationModel();
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// TODO: No external globals for now.
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if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) return 0;
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// TODO: Need more magic for ARM PIC.
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if (!isThumb && (RelocM == Reloc::PIC_)) return 0;
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// MachineConstantPool wants an explicit alignment.
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unsigned Align = TD.getPrefTypeAlignment(GV->getType());
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if (Align == 0) {
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// TODO: Figure out if this is correct.
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Align = TD.getTypeAllocSize(GV->getType());
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}
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// Grab index.
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unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : (Subtarget->isThumb() ? 4 : 8);
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unsigned Id = AFI->createConstPoolEntryUId();
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ARMConstantPoolValue *CPV = new ARMConstantPoolValue(GV, Id,
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ARMCP::CPValue, PCAdj);
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unsigned Idx = MCP.getConstantPoolIndex(CPV, Align);
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// Load value.
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MachineInstrBuilder MIB;
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unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
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@ -508,17 +508,17 @@ unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) {
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return ARMMaterializeGV(GV, VT);
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else if (isa<ConstantInt>(C))
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return ARMMaterializeInt(C, VT);
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return 0;
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}
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unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
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// Don't handle dynamic allocas.
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if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
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EVT VT;
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if (!isTypeLegal(AI->getType(), VT)) return false;
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DenseMap<const AllocaInst*, int>::iterator SI =
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FuncInfo.StaticAllocaMap.find(AI);
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@ -534,7 +534,7 @@ unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
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.addImm(0));
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return ResultReg;
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}
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return 0;
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}
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@ -694,7 +694,7 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg,
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// For now with the additions above the offset should be zero - thus we
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// can always fit into an i8.
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assert(Offset == 0 && "Offset not zero!");
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// The thumb and floating point instructions both take 2 operands, ARM takes
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// another register.
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if (isFloat || isThumb)
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@ -829,7 +829,7 @@ static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
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switch (Pred) {
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// Needs two compares...
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case CmpInst::FCMP_ONE:
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case CmpInst::FCMP_UEQ:
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case CmpInst::FCMP_UEQ:
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default:
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assert(false && "Unhandled CmpInst::Predicate!");
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return ARMCC::AL;
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@ -858,7 +858,7 @@ static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) {
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return ARMCC::PL;
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case CmpInst::ICMP_SLT:
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case CmpInst::FCMP_ULT:
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return ARMCC::LT;
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return ARMCC::LT;
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case CmpInst::ICMP_SLE:
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case CmpInst::FCMP_ULE:
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return ARMCC::LE;
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@ -886,13 +886,13 @@ bool ARMFastISel::SelectBranch(const Instruction *I) {
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unsigned CmpOpc = isThumb ? ARM::t2CMPri : ARM::CMPri;
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
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.addReg(CondReg).addImm(1));
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unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
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.addMBB(TBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
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FastEmitBranch(FBB, DL);
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FuncInfo.MBB->addSuccessor(TBB);
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return true;
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return true;
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}
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bool ARMFastISel::SelectCmp(const Instruction *I) {
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@ -928,7 +928,7 @@ bool ARMFastISel::SelectCmp(const Instruction *I) {
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// Get the compare predicate.
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ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate());
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// We may not handle every CC for now.
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if (ARMPred == ARMCC::AL) return false;
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@ -950,10 +950,10 @@ bool ARMFastISel::SelectCmp(const Instruction *I) {
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// Now set a register based on the comparison. Explicitly set the predicates
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// here.
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unsigned MovCCOpc = isThumb ? ARM::t2MOVCCi : ARM::MOVCCi;
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TargetRegisterClass *RC = isThumb ? ARM::rGPRRegisterClass
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TargetRegisterClass *RC = isThumb ? ARM::rGPRRegisterClass
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: ARM::GPRRegisterClass;
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unsigned DestReg = createResultReg(RC);
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Constant *Zero
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Constant *Zero
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= ConstantInt::get(Type::getInt32Ty(*Context), 0);
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unsigned ZeroReg = TargetMaterializeConstant(Zero);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg)
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@ -1005,25 +1005,25 @@ bool ARMFastISel::SelectFPTrunc(const Instruction *I) {
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bool ARMFastISel::SelectSIToFP(const Instruction *I) {
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// Make sure we have VFP.
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if (!Subtarget->hasVFP2()) return false;
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EVT DstVT;
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const Type *Ty = I->getType();
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if (!isTypeLegal(Ty, DstVT))
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return false;
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unsigned Op = getRegForValue(I->getOperand(0));
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if (Op == 0) return false;
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// The conversion routine works on fp-reg to fp-reg and the operand above
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// was an integer, move it to the fp registers if possible.
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unsigned FP = ARMMoveToFPReg(MVT::f32, Op);
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if (FP == 0) return false;
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unsigned Opc;
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if (Ty->isFloatTy()) Opc = ARM::VSITOS;
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else if (Ty->isDoubleTy()) Opc = ARM::VSITOD;
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else return 0;
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unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT));
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
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ResultReg)
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@ -1035,32 +1035,32 @@ bool ARMFastISel::SelectSIToFP(const Instruction *I) {
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bool ARMFastISel::SelectFPToSI(const Instruction *I) {
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// Make sure we have VFP.
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if (!Subtarget->hasVFP2()) return false;
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EVT DstVT;
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const Type *RetTy = I->getType();
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if (!isTypeLegal(RetTy, DstVT))
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return false;
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unsigned Op = getRegForValue(I->getOperand(0));
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if (Op == 0) return false;
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unsigned Opc;
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const Type *OpTy = I->getOperand(0)->getType();
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if (OpTy->isFloatTy()) Opc = ARM::VTOSIZS;
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else if (OpTy->isDoubleTy()) Opc = ARM::VTOSIZD;
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else return 0;
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// f64->s32 or f32->s32 both need an intermediate f32 reg.
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unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32));
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc),
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ResultReg)
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.addReg(Op));
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// This result needs to be in an integer register, but the conversion only
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// takes place in fp-regs.
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unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg);
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if (IntReg == 0) return false;
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UpdateValueMap(I, IntReg);
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return true;
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}
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@ -1102,8 +1102,8 @@ bool ARMFastISel::SelectSDiv(const Instruction *I) {
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// If we have integer div support we should have selected this automagically.
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// In case we have a real miss go ahead and return false and we'll pick
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// it up later.
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if (Subtarget->hasDivide()) return false;
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if (Subtarget->hasDivide()) return false;
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// Otherwise emit a libcall.
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RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
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if (VT == MVT::i8)
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@ -1117,7 +1117,7 @@ bool ARMFastISel::SelectSDiv(const Instruction *I) {
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else if (VT == MVT::i128)
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LC = RTLIB::SDIV_I128;
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assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
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return ARMEmitLibcall(I, LC);
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}
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@ -1257,7 +1257,7 @@ bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args,
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return false;
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}
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}
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return true;
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}
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@ -1285,20 +1285,20 @@ bool ARMFastISel::FinishCall(EVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
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Copy1).addReg(RVLocs[0].getLocReg());
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UsedRegs.push_back(RVLocs[0].getLocReg());
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unsigned Copy2 = createResultReg(CopyRC);
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
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Copy2).addReg(RVLocs[1].getLocReg());
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UsedRegs.push_back(RVLocs[1].getLocReg());
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EVT DestVT = RVLocs[0].getValVT();
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TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
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unsigned ResultReg = createResultReg(DstRC);
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(ARM::VMOVDRR), ResultReg)
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.addReg(Copy1).addReg(Copy2));
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// Finally update the result.
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// Finally update the result.
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UpdateValueMap(I, ResultReg);
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} else {
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assert(RVLocs.size() == 1 && "Can't handle non-double multi-reg retvals!");
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@ -1310,24 +1310,24 @@ bool ARMFastISel::FinishCall(EVT RetVT, SmallVectorImpl<unsigned> &UsedRegs,
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ResultReg).addReg(RVLocs[0].getLocReg());
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UsedRegs.push_back(RVLocs[0].getLocReg());
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// Finally update the result.
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// Finally update the result.
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UpdateValueMap(I, ResultReg);
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}
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}
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return true;
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return true;
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}
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// A quick function that will emit a call for a named libcall in F with the
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// vector of passed arguments for the Instruction in I. We can assume that we
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// can emit a call for any libcall we can produce. This is an abridged version
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// of the full call infrastructure since we won't need to worry about things
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// can emit a call for any libcall we can produce. This is an abridged version
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// of the full call infrastructure since we won't need to worry about things
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// like computed function pointers or strange arguments at call sites.
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// TODO: Try to unify this and the normal call bits for ARM, then try to unify
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// with X86.
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bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
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CallingConv::ID CC = TLI.getLibcallCallingConv(Call);
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// Handle *simple* calls for now.
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const Type *RetTy = I->getType();
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EVT RetVT;
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@ -1335,10 +1335,10 @@ bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
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RetVT = MVT::isVoid;
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else if (!isTypeLegal(RetTy, RetVT))
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return false;
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// For now we're using BLX etc on the assumption that we have v5t ops.
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if (!Subtarget->hasV5TOps()) return false;
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// Set up the argument vectors.
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SmallVector<Value*, 8> Args;
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SmallVector<unsigned, 8> ArgRegs;
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@ -1352,29 +1352,29 @@ bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
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Value *Op = I->getOperand(i);
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unsigned Arg = getRegForValue(Op);
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if (Arg == 0) return false;
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const Type *ArgTy = Op->getType();
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EVT ArgVT;
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if (!isTypeLegal(ArgTy, ArgVT)) return false;
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ISD::ArgFlagsTy Flags;
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unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
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Flags.setOrigAlign(OriginalAlignment);
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Args.push_back(Op);
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ArgRegs.push_back(Arg);
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ArgVTs.push_back(ArgVT);
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ArgFlags.push_back(Flags);
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}
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// Handle the arguments now that we've gotten them.
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SmallVector<unsigned, 4> RegArgs;
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unsigned NumBytes;
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if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
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return false;
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// Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops.
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// TODO: Turn this into the table of arm call ops.
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// TODO: Turn this into the table of arm call ops.
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MachineInstrBuilder MIB;
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unsigned CallOpc;
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if(isThumb)
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@ -1383,18 +1383,18 @@ bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
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CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
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MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
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.addExternalSymbol(TLI.getLibcallName(Call));
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// Add implicit physical register uses to the call.
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for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
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MIB.addReg(RegArgs[i]);
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// Finish off the call including any return values.
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SmallVector<unsigned, 4> UsedRegs;
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SmallVector<unsigned, 4> UsedRegs;
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if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
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// Set all unused physreg defs as dead.
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static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
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return true;
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}
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@ -1409,7 +1409,7 @@ bool ARMFastISel::SelectCall(const Instruction *I) {
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const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
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if (!GV || Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel()))
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return false;
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||||
|
||||
|
||||
// Check the calling convention.
|
||||
ImmutableCallSite CS(CI);
|
||||
CallingConv::ID CC = CS.getCallingConv();
|
||||
@ -1418,13 +1418,13 @@ bool ARMFastISel::SelectCall(const Instruction *I) {
|
||||
// errs() << "Can't handle calling convention: " << CC << "\n";
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
// Let SDISel handle vararg functions.
|
||||
const PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType());
|
||||
const FunctionType *FTy = cast<FunctionType>(PT->getElementType());
|
||||
if (FTy->isVarArg())
|
||||
return false;
|
||||
|
||||
|
||||
// Handle *simple* calls for now.
|
||||
const Type *RetTy = I->getType();
|
||||
EVT RetVT;
|
||||
@ -1432,11 +1432,11 @@ bool ARMFastISel::SelectCall(const Instruction *I) {
|
||||
RetVT = MVT::isVoid;
|
||||
else if (!isTypeLegal(RetTy, RetVT))
|
||||
return false;
|
||||
|
||||
|
||||
// For now we're using BLX etc on the assumption that we have v5t ops.
|
||||
// TODO: Maybe?
|
||||
if (!Subtarget->hasV5TOps()) return false;
|
||||
|
||||
|
||||
// Set up the argument vectors.
|
||||
SmallVector<Value*, 8> Args;
|
||||
SmallVector<unsigned, 8> ArgRegs;
|
||||
@ -1449,7 +1449,7 @@ bool ARMFastISel::SelectCall(const Instruction *I) {
|
||||
for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end();
|
||||
i != e; ++i) {
|
||||
unsigned Arg = getRegForValue(*i);
|
||||
|
||||
|
||||
if (Arg == 0)
|
||||
return false;
|
||||
ISD::ArgFlagsTy Flags;
|
||||
@ -1472,21 +1472,21 @@ bool ARMFastISel::SelectCall(const Instruction *I) {
|
||||
return false;
|
||||
unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy);
|
||||
Flags.setOrigAlign(OriginalAlignment);
|
||||
|
||||
|
||||
Args.push_back(*i);
|
||||
ArgRegs.push_back(Arg);
|
||||
ArgVTs.push_back(ArgVT);
|
||||
ArgFlags.push_back(Flags);
|
||||
}
|
||||
|
||||
|
||||
// Handle the arguments now that we've gotten them.
|
||||
SmallVector<unsigned, 4> RegArgs;
|
||||
unsigned NumBytes;
|
||||
if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, RegArgs, CC, NumBytes))
|
||||
return false;
|
||||
|
||||
|
||||
// Issue the call, BLXr9 for darwin, BLX otherwise. This uses V5 ops.
|
||||
// TODO: Turn this into the table of arm call ops.
|
||||
// TODO: Turn this into the table of arm call ops.
|
||||
MachineInstrBuilder MIB;
|
||||
unsigned CallOpc;
|
||||
if(isThumb)
|
||||
@ -1495,20 +1495,20 @@ bool ARMFastISel::SelectCall(const Instruction *I) {
|
||||
CallOpc = Subtarget->isTargetDarwin() ? ARM::BLr9 : ARM::BL;
|
||||
MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
|
||||
.addGlobalAddress(GV, 0, 0);
|
||||
|
||||
|
||||
// Add implicit physical register uses to the call.
|
||||
for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
|
||||
MIB.addReg(RegArgs[i]);
|
||||
|
||||
|
||||
// Finish off the call including any return values.
|
||||
SmallVector<unsigned, 4> UsedRegs;
|
||||
SmallVector<unsigned, 4> UsedRegs;
|
||||
if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes)) return false;
|
||||
|
||||
|
||||
// Set all unused physreg defs as dead.
|
||||
static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI);
|
||||
|
||||
|
||||
return true;
|
||||
|
||||
|
||||
}
|
||||
|
||||
// TODO: SoftFP support.
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user