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Merge isLoadFromStackSlot into one since it behaves the same regardless of sub-target.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77174 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2009-07-27 00:24:36 +00:00
parent 68e3c6ae49
commit dced03fc84
3 changed files with 23 additions and 49 deletions
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35
lib/Target/ARM/ARMBaseInstrInfo.cpp
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@@ -491,6 +491,7 @@ ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
SrcSubIdx = DstSubIdx = 0; // No sub-registers.
switch (MI.getOpcode()) {
default: break;
case ARM::FCPYS:
case ARM::FCPYD:
case ARM::VMOVD:
@@ -521,8 +522,10 @@ ARMBaseInstrInfo::isMoveInstr(const MachineInstr &MI,
unsigned
ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const {
unsigned oc = MI->getOpcode();
if (oc == getOpcode(ARMII::LDRrr)) {
switch (MI->getOpcode()) {
default: break;
case ARM::LDR:
case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
if (MI->getOperand(1).isFI() &&
MI->getOperand(2).isReg() &&
MI->getOperand(3).isImm() &&
@@ -531,22 +534,25 @@ ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
}
else if (oc == getOpcode(ARMII::LDRri)) {
break;
case ARM::t2LDRi12:
case ARM::tRestore:
if (MI->getOperand(1).isFI() &&
MI->getOperand(2).isImm() &&
MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
}
else if (oc == ARM::FLDD || oc == ARM::FLDS) {
break;
case ARM::FLDD:
case ARM::FLDS:
if (MI->getOperand(1).isFI() &&
MI->getOperand(2).isImm() &&
MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
break;
}
return 0;
@@ -555,8 +561,10 @@ ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
unsigned
ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
int &FrameIndex) const {
unsigned oc = MI->getOpcode();
if (oc == getOpcode(ARMII::STRrr)) {
switch (MI->getOpcode()) {
default: break;
case ARM::STR:
case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
if (MI->getOperand(1).isFI() &&
MI->getOperand(2).isReg() &&
MI->getOperand(3).isImm() &&
@@ -565,22 +573,25 @@ ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
}
else if (oc == getOpcode(ARMII::STRri)) {
break;
case ARM::t2STRi12:
case ARM::tSpill:
if (MI->getOperand(1).isFI() &&
MI->getOperand(2).isImm() &&
MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
}
else if (oc == ARM::FSTD || oc == ARM::FSTS) {
break;
case ARM::FSTD:
case ARM::FSTS:
if (MI->getOperand(1).isFI() &&
MI->getOperand(2).isImm() &&
MI->getOperand(2).getImm() == 0) {
FrameIndex = MI->getOperand(1).getIndex();
return MI->getOperand(0).getReg();
}
break;
}
return 0;