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Track IR ordering of SelectionDAG nodes 3/4.

Browse Source 
Remove the old IR ordering mechanism and switch to new one.  Fix unit
test failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182704 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick 2013-05-25 03:08:10 +00:00
parent ac6d9bec67
commit dd0fb018a7
17 changed files with 31 additions and 190 deletions
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11
include/llvm/CodeGen/SelectionDAG.h
View File

@ -33,7 +33,6 @@ class AliasAnalysis;
class MachineConstantPoolValue;
class MachineFunction;
class MDNode;
class SDNodeOrdering;
class SDDbgValue;
class TargetLowering;
class TargetSelectionDAGInfo;
@ -166,10 +165,6 @@ class SelectionDAG {
/// SelectionDAG.
BumpPtrAllocator Allocator;
/// SDNodeOrdering - The ordering of the SDNodes. It roughly corresponds to
/// the ordering of the original LLVM instructions.
SDNodeOrdering *Ordering;
/// DbgInfo - Tracks dbg_value information through SDISel.
SDDbgInfo *DbgInfo;
@ -950,12 +945,6 @@ public:
}
}
/// AssignOrdering - Assign an order to the SDNode.
void AssignOrdering(const SDNode *SD, unsigned Order);
/// GetOrdering - Get the order for the SDNode.
unsigned GetOrdering(const SDNode *SD) const;
/// AddDbgValue - Add a dbg_value SDNode. If SD is non-null that means the
/// value is produced by SD.
void AddDbgValue(SDDbgValue *DB, SDNode *SD, bool isParameter);

26
lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
View File

@ -735,9 +735,6 @@ void DAGTypeLegalizer::SetPromotedInteger(SDValue Op, SDValue Result) {
SDValue &OpEntry = PromotedIntegers[Op];
assert(OpEntry.getNode() == 0 && "Node is already promoted!");
OpEntry = Result;
// Propagate node ordering
DAG.AssignOrdering(Result.getNode(), DAG.GetOrdering(Op.getNode()));
}
void DAGTypeLegalizer::SetSoftenedFloat(SDValue Op, SDValue Result) {
@ -749,9 +746,6 @@ void DAGTypeLegalizer::SetSoftenedFloat(SDValue Op, SDValue Result) {
SDValue &OpEntry = SoftenedFloats[Op];
assert(OpEntry.getNode() == 0 && "Node is already converted to integer!");
OpEntry = Result;
// Propagate node ordering
DAG.AssignOrdering(Result.getNode(), DAG.GetOrdering(Op.getNode()));
}
void DAGTypeLegalizer::SetScalarizedVector(SDValue Op, SDValue Result) {
@ -766,9 +760,6 @@ void DAGTypeLegalizer::SetScalarizedVector(SDValue Op, SDValue Result) {
SDValue &OpEntry = ScalarizedVectors[Op];
assert(OpEntry.getNode() == 0 && "Node is already scalarized!");
OpEntry = Result;
// Propagate node ordering
DAG.AssignOrdering(Result.getNode(), DAG.GetOrdering(Op.getNode()));
}
void DAGTypeLegalizer::GetExpandedInteger(SDValue Op, SDValue &Lo,
@ -796,10 +787,6 @@ void DAGTypeLegalizer::SetExpandedInteger(SDValue Op, SDValue Lo,
assert(Entry.first.getNode() == 0 && "Node already expanded");
Entry.first = Lo;
Entry.second = Hi;
// Propagate ordering
DAG.AssignOrdering(Lo.getNode(), DAG.GetOrdering(Op.getNode()));
DAG.AssignOrdering(Hi.getNode(), DAG.GetOrdering(Op.getNode()));
}
void DAGTypeLegalizer::GetExpandedFloat(SDValue Op, SDValue &Lo,
@ -827,10 +814,6 @@ void DAGTypeLegalizer::SetExpandedFloat(SDValue Op, SDValue Lo,
assert(Entry.first.getNode() == 0 && "Node already expanded");
Entry.first = Lo;
Entry.second = Hi;
// Propagate ordering
DAG.AssignOrdering(Lo.getNode(), DAG.GetOrdering(Op.getNode()));
DAG.AssignOrdering(Hi.getNode(), DAG.GetOrdering(Op.getNode()));
}
void DAGTypeLegalizer::GetSplitVector(SDValue Op, SDValue &Lo,
@ -860,10 +843,6 @@ void DAGTypeLegalizer::SetSplitVector(SDValue Op, SDValue Lo,
assert(Entry.first.getNode() == 0 && "Node already split");
Entry.first = Lo;
Entry.second = Hi;
// Propagate ordering
DAG.AssignOrdering(Lo.getNode(), DAG.GetOrdering(Op.getNode()));
DAG.AssignOrdering(Hi.getNode(), DAG.GetOrdering(Op.getNode()));
}
void DAGTypeLegalizer::SetWidenedVector(SDValue Op, SDValue Result) {
@ -875,9 +854,6 @@ void DAGTypeLegalizer::SetWidenedVector(SDValue Op, SDValue Result) {
SDValue &OpEntry = WidenedVectors[Op];
assert(OpEntry.getNode() == 0 && "Node already widened!");
OpEntry = Result;
// Propagate node ordering
DAG.AssignOrdering(Result.getNode(), DAG.GetOrdering(Op.getNode()));
}
@ -945,8 +921,6 @@ bool DAGTypeLegalizer::CustomLowerNode(SDNode *N, EVT VT, bool LegalizeResult) {
"Custom lowering returned the wrong number of results!");
for (unsigned i = 0, e = Results.size(); i != e; ++i) {
ReplaceValueWith(SDValue(N, i), Results[i]);
// Propagate node ordering
DAG.AssignOrdering(Results[i].getNode(), DAG.GetOrdering(N));
}
return true;
}

56
lib/CodeGen/SelectionDAG/SDNodeOrdering.h
View File

@ -1,56 +0,0 @@
//===-- llvm/CodeGen/SDNodeOrdering.h - SDNode Ordering ---------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file declares the SDNodeOrdering class.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_CODEGEN_SDNODEORDERING_H
#define LLVM_CODEGEN_SDNODEORDERING_H
#include "llvm/ADT/DenseMap.h"
namespace llvm {
class SDNode;
/// SDNodeOrdering - Maps a unique (monotonically increasing) value to each
/// SDNode that roughly corresponds to the ordering of the original LLVM
/// instruction. This is used for turning off scheduling, because we'll forgo
/// the normal scheduling algorithms and output the instructions according to
/// this ordering.
class SDNodeOrdering {
DenseMap<const SDNode*, unsigned> OrderMap;
void operator=(const SDNodeOrdering&) LLVM_DELETED_FUNCTION;
SDNodeOrdering(const SDNodeOrdering&) LLVM_DELETED_FUNCTION;
public:
SDNodeOrdering() {}
void add(const SDNode *Node, unsigned NewOrder) {
unsigned &OldOrder = OrderMap[Node];
if (OldOrder == 0 || (OldOrder > 0 && NewOrder < OldOrder))
OldOrder = NewOrder;
}
void remove(const SDNode *Node) {
DenseMap<const SDNode*, unsigned>::iterator Itr = OrderMap.find(Node);
if (Itr != OrderMap.end())
OrderMap.erase(Itr);
}
void clear() {
OrderMap.clear();
}
unsigned getOrder(const SDNode *Node) {
return OrderMap[Node];
}
};
} // end llvm namespace
#endif

2
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
View File

@ -1692,7 +1692,7 @@ public:
unsigned getNodeOrdering(const SUnit *SU) const {
if (!SU->getNode()) return 0;
return scheduleDAG->DAG->GetOrdering(SU->getNode());
return SU->getNode()->getIROrder();
}
bool empty() const { return Queue.empty(); }

2
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
View File

@ -736,7 +736,7 @@ static void ProcessSourceNode(SDNode *N, SelectionDAG *DAG,
DenseMap<SDValue, unsigned> &VRBaseMap,
SmallVector<std::pair<unsigned, MachineInstr*>, 32> &Orders,
SmallSet<unsigned, 8> &Seen) {
unsigned Order = DAG->GetOrdering(N);
unsigned Order = N->getIROrder();
if (!Order || !Seen.insert(Order)) {
// Process any valid SDDbgValues even if node does not have any order
// assigned.

37
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -13,7 +13,6 @@
#include "llvm/CodeGen/SelectionDAG.h"
#include "SDNodeDbgValue.h"
#include "SDNodeOrdering.h"
#include "llvm/ADT/SetVector.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/SmallSet.h"
@ -636,9 +635,6 @@ void SelectionDAG::DeallocateNode(SDNode *N) {
NodeAllocator.Deallocate(AllNodes.remove(N));
// Remove the ordering of this node.
Ordering->remove(N);
// If any of the SDDbgValue nodes refer to this SDNode, invalidate them.
ArrayRef<SDDbgValue*> DbgVals = DbgInfo->getSDDbgValues(N);
for (unsigned i = 0, e = DbgVals.size(); i != e; ++i)
@ -876,9 +872,8 @@ SelectionDAG::SelectionDAG(const TargetMachine &tm, CodeGenOpt::Level OL)
: TM(tm), TLI(*tm.getTargetLowering()), TSI(*tm.getSelectionDAGInfo()),
TTI(0), OptLevel(OL), EntryNode(ISD::EntryToken, 0, DebugLoc(),
getVTList(MVT::Other)),
Root(getEntryNode()), Ordering(0), UpdateListeners(0) {
Root(getEntryNode()), UpdateListeners(0) {
AllNodes.push_back(&EntryNode);
Ordering = new SDNodeOrdering();
DbgInfo = new SDDbgInfo();
}
@ -891,7 +886,6 @@ void SelectionDAG::init(MachineFunction &mf, const TargetTransformInfo *tti) {
SelectionDAG::~SelectionDAG() {
assert(!UpdateListeners && "Dangling registered DAGUpdateListeners");
allnodes_clear();
delete Ordering;
delete DbgInfo;
}
@ -918,7 +912,6 @@ void SelectionDAG::clear() {
EntryNode.UseList = 0;
AllNodes.push_back(&EntryNode);
Root = getEntryNode();
Ordering->clear();
DbgInfo->clear();
}
@ -3470,10 +3463,10 @@ static SDValue getMemsetStringVal(EVT VT, SDLoc dl, SelectionDAG &DAG,
/// getMemBasePlusOffset - Returns base and offset node for the
///
static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset,
static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset, SDLoc dl,
SelectionDAG &DAG) {
EVT VT = Base.getValueType();
return DAG.getNode(ISD::ADD, SDLoc(Base),
return DAG.getNode(ISD::ADD, dl,
VT, Base, DAG.getConstant(Offset, VT));
}
@ -3687,7 +3680,7 @@ static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, SDLoc dl,
Value = getMemsetStringVal(VT, dl, DAG, TLI, Str.substr(SrcOff));
if (Value.getNode())
Store = DAG.getStore(Chain, dl, Value,
getMemBasePlusOffset(Dst, DstOff, DAG),
getMemBasePlusOffset(Dst, DstOff, dl, DAG),
DstPtrInfo.getWithOffset(DstOff), isVol,
false, Align);
}
@ -3701,11 +3694,11 @@ static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, SDLoc dl,
EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT);
assert(NVT.bitsGE(VT));
Value = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Chain,
getMemBasePlusOffset(Src, SrcOff, DAG),
getMemBasePlusOffset(Src, SrcOff, dl, DAG),
SrcPtrInfo.getWithOffset(SrcOff), VT, isVol, false,
MinAlign(SrcAlign, SrcOff));
Store = DAG.getTruncStore(Chain, dl, Value,
getMemBasePlusOffset(Dst, DstOff, DAG),
getMemBasePlusOffset(Dst, DstOff, dl, DAG),
DstPtrInfo.getWithOffset(DstOff), VT, isVol,
false, Align);
}
@ -3774,7 +3767,7 @@ static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, SDLoc dl,
SDValue Value, Store;
Value = DAG.getLoad(VT, dl, Chain,
getMemBasePlusOffset(Src, SrcOff, DAG),
getMemBasePlusOffset(Src, SrcOff, dl, DAG),
SrcPtrInfo.getWithOffset(SrcOff), isVol,
false, false, SrcAlign);
LoadValues.push_back(Value);
@ -3790,7 +3783,7 @@ static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, SDLoc dl,
SDValue Value, Store;
Store = DAG.getStore(Chain, dl, LoadValues[i],
getMemBasePlusOffset(Dst, DstOff, DAG),
getMemBasePlusOffset(Dst, DstOff, dl, DAG),
DstPtrInfo.getWithOffset(DstOff), isVol, false, Align);
OutChains.push_back(Store);
DstOff += VTSize;
@ -3872,7 +3865,7 @@ static SDValue getMemsetStores(SelectionDAG &DAG, SDLoc dl,
}
assert(Value.getValueType() == VT && "Value with wrong type.");
SDValue Store = DAG.getStore(Chain, dl, Value,
getMemBasePlusOffset(Dst, DstOff, DAG),
getMemBasePlusOffset(Dst, DstOff, dl, DAG),
DstPtrInfo.getWithOffset(DstOff),
isVol, false, Align);
OutChains.push_back(Store);
@ -5865,18 +5858,6 @@ unsigned SelectionDAG::AssignTopologicalOrder() {
return DAGSize;
}
/// AssignOrdering - Assign an order to the SDNode.
void SelectionDAG::AssignOrdering(const SDNode *SD, unsigned Order) {
assert(SD && "Trying to assign an order to a null node!");
Ordering->add(SD, Order);
}
/// GetOrdering - Get the order for the SDNode.
unsigned SelectionDAG::GetOrdering(const SDNode *SD) const {
assert(SD && "Trying to get the order of a null node!");
return Ordering->getOrder(SD);
}
/// AddDbgValue - Add a dbg_value SDNode. If SD is non-null that means the
/// value is produced by SD.
void SelectionDAG::AddDbgValue(SDDbgValue *DB, SDNode *SD, bool isParameter) {

41
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
View File

@ -938,19 +938,13 @@ SDValue SelectionDAGBuilder::getControlRoot() {
return Root;
}
void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) {
if (DAG.GetOrdering(Node) != 0) return; // Already has ordering.
DAG.AssignOrdering(Node, SDNodeOrder);
for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I)
AssignOrderingToNode(Node->getOperand(I).getNode());
}
void SelectionDAGBuilder::visit(const Instruction &I) {
// Set up outgoing PHI node register values before emitting the terminator.
if (isa<TerminatorInst>(&I))
HandlePHINodesInSuccessorBlocks(I.getParent());
++SDNodeOrder;
CurInst = &I;
visit(I.getOpcode(), I);
@ -975,12 +969,6 @@ void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) {
case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
#include "llvm/IR/Instruction.def"
}
// Assign the ordering to the freshly created DAG nodes.
if (NodeMap.count(&I)) {
++SDNodeOrder;
AssignOrderingToNode(getValue(&I).getNode());
}
}
// resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V,
@ -3397,8 +3385,6 @@ void SelectionDAGBuilder::visitStore(const StoreInst &I) {
SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurSDLoc(),
MVT::Other, &Chains[0], ChainI);
++SDNodeOrder;
AssignOrderingToNode(StoreNode.getNode());
DAG.setRoot(StoreNode);
}
@ -3652,12 +3638,6 @@ void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I,
}
setValue(&I, Result);
} else {
// Assign order to result here. If the intrinsic does not produce a result,
// it won't be mapped to a SDNode and visit() will not assign it an order
// number.
++SDNodeOrder;
AssignOrderingToNode(Result.getNode());
}
}
@ -4525,12 +4505,6 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
return 0;
}
// Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
// but do not always have a corresponding SDNode built. The SDNodeOrder
// absolute, but not relative, values are different depending on whether
// debug info exists.
++SDNodeOrder;
// Check if address has undef value.
if (isa<UndefValue>(Address) ||
(Address->use_empty() && !isa<Argument>(Address))) {
@ -4610,11 +4584,6 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
if (!V)
return 0;
// Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder
// but do not always have a corresponding SDNode built. The SDNodeOrder
// absolute, but not relative, values are different depending on whether
// debug info exists.
++SDNodeOrder;
SDDbgValue *SDV;
if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) {
SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder);
@ -5347,18 +5316,12 @@ void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
&Values[0], Values.size()));
}
// Assign order to nodes here. If the call does not produce a result, it won't
// be mapped to a SDNode and visit() will not assign it an order number.
if (!Result.second.getNode()) {
// As a special case, a null chain means that a tail call has been emitted and
// the DAG root is already updated.
HasTailCall = true;
++SDNodeOrder;
AssignOrderingToNode(DAG.getRoot().getNode());
} else {
DAG.setRoot(Result.second);
++SDNodeOrder;
AssignOrderingToNode(Result.second.getNode());
}
if (LandingPad) {

5
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
View File

@ -377,11 +377,6 @@ public:
void CopyValueToVirtualRegister(const Value *V, unsigned Reg);
/// AssignOrderingToNode - Assign an ordering to the node. The order is gotten
/// from how the code appeared in the source. The ordering is used by the
/// scheduler to effectively turn off scheduling.
void AssignOrderingToNode(const SDNode *Node);
void visit(const Instruction &I);
void visit(unsigned Opcode, const User &I);

4
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -624,6 +624,7 @@ void SelectionDAGISel::CodeGenAndEmitDAG() {
DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber
<< " '" << BlockName << "'\n"; CurDAG->dump());
}
{
@ -790,9 +791,6 @@ void SelectionDAGISel::DoInstructionSelection() {
continue;
// Replace node.
if (ResNode) {
// Propagate ordering
CurDAG->AssignOrdering(ResNode, CurDAG->GetOrdering(Node));
ReplaceUses(Node, ResNode);
}

6
lib/Target/NVPTX/NVPTXISelLowering.cpp
View File

@ -1145,14 +1145,14 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
false,
TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
if (p.getNode())
DAG.AssignOrdering(p.getNode(), idx + 1);
p.getNode()->setIROrder(idx + 1);
InVals.push_back(p);
} else {
// If no ABI, just move the param symbol
SDValue Arg = getParamSymbol(DAG, idx, ObjectVT);
SDValue p = DAG.getNode(NVPTXISD::MoveParam, dl, ObjectVT, Arg);
if (p.getNode())
DAG.AssignOrdering(p.getNode(), idx + 1);
p.getNode()->setIROrder(idx + 1);
InVals.push_back(p);
}
continue;
@ -1169,7 +1169,7 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
SDValue Arg = getParamSymbol(DAG, idx, getPointerTy());
SDValue p = DAG.getNode(NVPTXISD::MoveParam, dl, ObjectVT, Arg);
if (p.getNode())
DAG.AssignOrdering(p.getNode(), idx + 1);
p.getNode()->setIROrder(idx + 1);
if (isKernel)
InVals.push_back(p);
else {

3
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -2335,9 +2335,6 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
DEBUG(dbgs() << "=> "; ResHi.getNode()->dump(CurDAG); dbgs() << '\n');
}
// Propagate ordering to the last node, for now.
CurDAG->AssignOrdering(InFlag.getNode(), CurDAG->GetOrdering(Node));
return NULL;
}

6
test/CodeGen/AArch64/sincos-expansion.ll
View File

@ -3,8 +3,8 @@
define float @test_sincos_f32(float %f) {
%sin = call float @sinf(float %f) readnone
%cos = call float @cosf(float %f) readnone
; CHECK: bl cosf
; CHECK: bl sinf
; CHECK: bl cosf
%val = fadd float %sin, %cos
ret float %val
}
@ -13,8 +13,8 @@ define double @test_sincos_f64(double %f) {
%sin = call double @sin(double %f) readnone
%cos = call double @cos(double %f) readnone
%val = fadd double %sin, %cos
; CHECK: bl cos
; CHECK: bl sin
; CHECK: bl cos
ret double %val
}
@ -22,8 +22,8 @@ define fp128 @test_sincos_f128(fp128 %f) {
%sin = call fp128 @sinl(fp128 %f) readnone
%cos = call fp128 @cosl(fp128 %f) readnone
%val = fadd fp128 %sin, %cos
; CHECK: bl cosl
; CHECK: bl sinl
; CHECK: bl cosl
ret fp128 %val
}

2
test/CodeGen/ARM/2011-08-25-ldmia_ret.ll
View File

@ -42,7 +42,7 @@ if.then: ; preds = %land.lhs.true
; If-convert the return
; CHECK: it ne
; Fold the CSR+return into a pop
; CHECK: popne {r4, r5, r7, pc}
; CHECK: pop {r4, r5, r6, r7, pc}
sw.bb18:
%call20 = tail call i32 @bar(i32 %in2) nounwind
switch i32 %call20, label %sw.default56 [

8
test/CodeGen/ARM/fast-isel-pic.ll
View File

@ -15,7 +15,7 @@ entry:
; THUMB-ELF: LoadGV
; THUMB-ELF: ldr.n r[[reg0:[0-9]+]],
; THUMB-ELF: ldr.n r[[reg1:[0-9]+]],
; THUMB-ELF: ldr r[[reg0]], [r[[reg1]], r[[reg0]]]
; THUMB-ELF: ldr r[[reg0]], [r[[reg0]], r[[reg1]]]
; ARM: LoadGV
; ARM: ldr [[reg1:r[0-9]+]],
; ARM: add [[reg1]], pc, [[reg1]]
@ -26,7 +26,7 @@ entry:
; ARMv7-ELF: LoadGV
; ARMv7-ELF: ldr r[[reg2:[0-9]+]],
; ARMv7-ELF: ldr r[[reg3:[0-9]+]],
; ARMv7-ELF: ldr r[[reg2]], [r[[reg3]], r[[reg2]]]
; ARMv7-ELF: ldr r[[reg2]], [r[[reg2]], r[[reg3]]]
%tmp = load i32* @g
ret i32 %tmp
}
@ -43,7 +43,7 @@ entry:
; THUMB-ELF: LoadIndirectSymbol
; THUMB-ELF: ldr.n r[[reg3:[0-9]+]],
; THUMB-ELF: ldr.n r[[reg4:[0-9]+]],
; THUMB-ELF: ldr r[[reg3]], [r[[reg4]], r[[reg3]]]
; THUMB-ELF: ldr r[[reg3]], [r[[reg3]], r[[reg4]]]
; ARM: LoadIndirectSymbol
; ARM: ldr [[reg4:r[0-9]+]],
; ARM: ldr [[reg4]], [pc, [[reg4]]]
@ -55,7 +55,7 @@ entry:
; ARMv7-ELF: LoadIndirectSymbol
; ARMv7-ELF: ldr r[[reg5:[0-9]+]],
; ARMv7-ELF: ldr r[[reg6:[0-9]+]],
; ARMv7-ELF: ldr r[[reg5]], [r[[reg6]], r[[reg5]]]
; ARMv7-ELF: ldr r[[reg5]], [r[[reg5]], r[[reg6]]]
%tmp = load i32* @i
ret i32 %tmp
}

4
test/CodeGen/X86/sincos-opt.ll
View File

@ -19,8 +19,8 @@ entry:
; OSX_SINCOS: addss %xmm0, %xmm1
; OSX_NOOPT: test1
; OSX_NOOPT: callq _cosf
; OSX_NOOPT: callq _sinf
; OSX_NOOPT: callq _cosf
%call = tail call float @sinf(float %x) nounwind readnone
%call1 = tail call float @cosf(float %x) nounwind readnone
%add = fadd float %call, %call1
@ -39,8 +39,8 @@ entry:
; OSX_SINCOS: addsd %xmm1, %xmm0
; OSX_NOOPT: test2
; OSX_NOOPT: callq _cos
; OSX_NOOPT: callq _sin
; OSX_NOOPT: callq _cos
%call = tail call double @sin(double %x) nounwind readnone
%call1 = tail call double @cos(double %x) nounwind readnone
%add = fadd double %call, %call1

4
test/CodeGen/X86/win32_sret.ll
View File

@ -115,8 +115,8 @@ entry:
; Load the address of the result and put it onto stack
; (through %ecx in the -O0 build).
; WIN32: leal {{[0-9]+}}(%esp), %eax
; WIN32: movl %eax, (%e{{[sc][px]}})
; WIN32: leal {{[0-9]+}}(%esp), %e{{[a-d]}}x
; WIN32: movl %e{{[a-d]}}x, (%e{{([a-d]x)|(sp)}})
; The this pointer goes to ECX.
; WIN32-NEXT: leal {{[0-9]+}}(%esp), %ecx

4
test/Transforms/LoopStrengthReduce/X86/2011-11-29-postincphi.ll
View File

@ -11,9 +11,9 @@ declare i1 @check() nounwind
; Check that LSR did something close to the behavior at the time of the bug.
; CHECK: @sqlite3DropTriggerPtr
; CHECK: incq %rax
; CHECK: incq %r{{[a-d]}}x
; CHECK: jne
; CHECK: decq %rax
; CHECK: decq %r{{[a-d]}}x
; CHECK: ret
define i64 @sqlite3DropTriggerPtr() nounwind {
bb: