mirror of
https://github.com/c64scene-ar/llvm-6502.git
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[ms-inline asm] Extend support for parsing Intel bracketed memory operands that
have an arbitrary ordering of the base register, index register and displacement. rdar://12527141 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172484 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier
parent
510db8bcb9
commit
dd2e895022
@ -684,115 +684,298 @@ static unsigned getIntelMemOperandSize(StringRef OpStr) {
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return Size;
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}
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enum IntelBracExprState {
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IBES_START,
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IBES_LBRAC,
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IBES_RBRAC,
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IBES_REGISTER,
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IBES_REGISTER_STAR,
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IBES_REGISTER_STAR_INTEGER,
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IBES_INTEGER,
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IBES_INTEGER_STAR,
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IBES_INDEX_REGISTER,
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IBES_IDENTIFIER,
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IBES_DISP_EXPR,
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IBES_MINUS,
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IBES_ERROR
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};
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class IntelBracExprStateMachine {
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IntelBracExprState State;
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unsigned BaseReg, IndexReg, Scale;
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int64_t Disp;
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unsigned TmpReg;
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int64_t TmpInteger;
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bool isPlus;
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public:
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IntelBracExprStateMachine(MCAsmParser &parser) :
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State(IBES_START), BaseReg(0), IndexReg(0), Scale(1), Disp(0),
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TmpReg(0), TmpInteger(0), isPlus(true) {}
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unsigned getBaseReg() { return BaseReg; }
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unsigned getIndexReg() { return IndexReg; }
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unsigned getScale() { return Scale; }
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int64_t getDisp() { return Disp; }
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bool isValidEndState() { return State == IBES_RBRAC; }
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void onPlus() {
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switch (State) {
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default:
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State = IBES_ERROR;
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break;
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case IBES_INTEGER:
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State = IBES_START;
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if (isPlus)
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Disp += TmpInteger;
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else
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Disp -= TmpInteger;
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break;
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case IBES_REGISTER:
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State = IBES_START;
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// If we already have a BaseReg, then assume this is the IndexReg with a
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// scale of 1.
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if (!BaseReg) {
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BaseReg = TmpReg;
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} else {
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assert (!IndexReg && "BaseReg/IndexReg already set!");
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IndexReg = TmpReg;
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Scale = 1;
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}
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break;
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case IBES_INDEX_REGISTER:
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State = IBES_START;
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break;
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}
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isPlus = true;
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}
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void onMinus() {
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switch (State) {
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default:
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State = IBES_ERROR;
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break;
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case IBES_START:
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State = IBES_MINUS;
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break;
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case IBES_INTEGER:
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State = IBES_START;
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if (isPlus)
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Disp += TmpInteger;
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else
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Disp -= TmpInteger;
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break;
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case IBES_REGISTER:
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State = IBES_START;
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// If we already have a BaseReg, then assume this is the IndexReg with a
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// scale of 1.
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if (!BaseReg) {
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BaseReg = TmpReg;
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} else {
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assert (!IndexReg && "BaseReg/IndexReg already set!");
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IndexReg = TmpReg;
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Scale = 1;
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}
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break;
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case IBES_INDEX_REGISTER:
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State = IBES_START;
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break;
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}
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isPlus = false;
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}
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void onRegister(unsigned Reg) {
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switch (State) {
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default:
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State = IBES_ERROR;
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break;
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case IBES_START:
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State = IBES_REGISTER;
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TmpReg = Reg;
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break;
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case IBES_INTEGER_STAR:
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assert (!IndexReg && "IndexReg already set!");
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State = IBES_INDEX_REGISTER;
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IndexReg = Reg;
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Scale = TmpInteger;
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break;
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}
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}
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void onDispExpr() {
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switch (State) {
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default:
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State = IBES_ERROR;
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break;
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case IBES_START:
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State = IBES_DISP_EXPR;
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break;
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}
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}
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void onInteger(int64_t TmpInt) {
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switch (State) {
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default:
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State = IBES_ERROR;
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break;
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case IBES_START:
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State = IBES_INTEGER;
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TmpInteger = TmpInt;
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break;
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case IBES_MINUS:
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State = IBES_INTEGER;
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TmpInteger = TmpInt;
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break;
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case IBES_REGISTER_STAR:
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assert (!IndexReg && "IndexReg already set!");
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State = IBES_INDEX_REGISTER;
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IndexReg = TmpReg;
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Scale = TmpInt;
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break;
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}
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}
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void onStar() {
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switch (State) {
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default:
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State = IBES_ERROR;
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break;
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case IBES_INTEGER:
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State = IBES_INTEGER_STAR;
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break;
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case IBES_REGISTER:
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State = IBES_REGISTER_STAR;
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break;
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}
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}
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void onLBrac() {
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switch (State) {
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default:
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State = IBES_ERROR;
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break;
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case IBES_RBRAC:
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State = IBES_START;
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isPlus = true;
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break;
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}
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}
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void onRBrac() {
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switch (State) {
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default:
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State = IBES_ERROR;
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break;
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case IBES_DISP_EXPR:
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State = IBES_RBRAC;
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break;
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case IBES_INTEGER:
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State = IBES_RBRAC;
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if (isPlus)
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Disp += TmpInteger;
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else
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Disp -= TmpInteger;
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break;
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case IBES_REGISTER:
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State = IBES_RBRAC;
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// If we already have a BaseReg, then assume this is the IndexReg with a
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// scale of 1.
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if (!BaseReg) {
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BaseReg = TmpReg;
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} else {
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assert (!IndexReg && "BaseReg/IndexReg already set!");
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IndexReg = TmpReg;
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Scale = 1;
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}
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break;
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case IBES_INDEX_REGISTER:
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State = IBES_RBRAC;
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break;
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}
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}
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};
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X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg,
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unsigned Size) {
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unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
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const AsmToken &Tok = Parser.getTok();
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SMLoc Start = Tok.getLoc(), End = Tok.getEndLoc();
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const MCExpr *Disp = MCConstantExpr::Create(0, getContext());
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// Parse [ BaseReg + Scale*IndexReg + Disp ] or [ symbol ]
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// Eat '['
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if (getLexer().isNot(AsmToken::LBrac))
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return ErrorOperand(Start, "Expected '[' token!");
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Parser.Lex();
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unsigned TmpReg = 0;
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// Try to handle '[' 'symbol' ']'
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if (getLexer().is(AsmToken::Identifier)) {
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// Parse BaseReg
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if (ParseRegister(BaseReg, Start, End)) {
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// Handle '[' 'symbol' ']'
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if (getParser().ParseExpression(Disp, End)) return 0;
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if (ParseRegister(TmpReg, Start, End)) {
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const MCExpr *Disp;
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if (getParser().ParseExpression(Disp, End))
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return 0;
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if (getLexer().isNot(AsmToken::RBrac))
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return ErrorOperand(Parser.getTok().getLoc(), "Expected ']' token!");
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End = Parser.getTok().getEndLoc();
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Parser.Lex();
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return X86Operand::CreateMem(Disp, Start, End, Size);
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}
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} else if (getLexer().is(AsmToken::Integer)) {
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int64_t Val = Tok.getIntVal();
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Parser.Lex();
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SMLoc Loc = Tok.getLoc();
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if (getLexer().is(AsmToken::RBrac)) {
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// Handle '[' number ']'
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End = Parser.getTok().getEndLoc();
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Parser.Lex();
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const MCExpr *Disp = MCConstantExpr::Create(Val, getContext());
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if (SegReg)
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return X86Operand::CreateMem(SegReg, Disp, 0, 0, Scale,
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Start, End, Size);
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return X86Operand::CreateMem(Disp, Start, End, Size);
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} else if (getLexer().is(AsmToken::Star)) {
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// Handle '[' Scale*IndexReg ']'
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Parser.Lex();
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SMLoc IdxRegLoc = Tok.getLoc();
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if (ParseRegister(IndexReg, IdxRegLoc, End))
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return ErrorOperand(IdxRegLoc, "Expected register");
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Scale = Val;
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} else
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return ErrorOperand(Loc, "Unexpected token");
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}
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// Parse ][ as a plus.
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bool ExpectRBrac = true;
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if (getLexer().is(AsmToken::RBrac)) {
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ExpectRBrac = false;
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End = Parser.getTok().getEndLoc();
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Parser.Lex();
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}
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// Parse [ BaseReg + Scale*IndexReg + Disp ].
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bool Done = false;
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IntelBracExprStateMachine SM(Parser);
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if (getLexer().is(AsmToken::Plus) || getLexer().is(AsmToken::Minus) ||
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getLexer().is(AsmToken::LBrac)) {
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ExpectRBrac = true;
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bool isPlus = getLexer().is(AsmToken::Plus) ||
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getLexer().is(AsmToken::LBrac);
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Parser.Lex();
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SMLoc PlusLoc = Tok.getLoc();
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if (getLexer().is(AsmToken::Integer)) {
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// If we parsed a register, then the end loc has already been set and
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// the identifier has already been lexed. We also need to update the
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// state.
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if (TmpReg)
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SM.onRegister(TmpReg);
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const MCExpr *Disp = 0;
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while (!Done) {
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bool UpdateLocLex = true;
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// The period in the dot operator (e.g., [ebx].foo.bar) is parsed as an
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// identifier. Don't try an parse it as a register.
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if (Tok.getString().startswith("."))
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break;
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switch (getLexer().getKind()) {
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default: {
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if (SM.isValidEndState()) {
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Done = true;
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break;
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}
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return ErrorOperand(Tok.getLoc(), "Unexpected token!");
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}
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case AsmToken::Identifier: {
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// This could be a register or a displacement expression.
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if(!ParseRegister(TmpReg, Start, End)) {
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SM.onRegister(TmpReg);
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UpdateLocLex = false;
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break;
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} else if (!getParser().ParseExpression(Disp, End)) {
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SM.onDispExpr();
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UpdateLocLex = false;
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break;
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}
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return ErrorOperand(Tok.getLoc(), "Unexpected identifier!");
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}
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case AsmToken::Integer: {
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int64_t Val = Tok.getIntVal();
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Parser.Lex();
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if (getLexer().is(AsmToken::Star)) {
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Parser.Lex();
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SMLoc IdxRegLoc = Tok.getLoc();
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if (ParseRegister(IndexReg, IdxRegLoc, End))
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return ErrorOperand(IdxRegLoc, "Expected register");
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Scale = Val;
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} else if (getLexer().is(AsmToken::RBrac)) {
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const MCExpr *ValExpr = MCConstantExpr::Create(Val, getContext());
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Disp = isPlus ? ValExpr : MCConstantExpr::Create(0-Val, getContext());
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} else
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return ErrorOperand(PlusLoc, "unexpected token after +");
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} else if (getLexer().is(AsmToken::Identifier)) {
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// This could be an index register or a displacement expression.
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if (!IndexReg)
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ParseRegister(IndexReg, Start, End);
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else if (getParser().ParseExpression(Disp, End))
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return 0;
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SM.onInteger(Val);
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break;
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}
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case AsmToken::Plus: SM.onPlus(); break;
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case AsmToken::Minus: SM.onMinus(); break;
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case AsmToken::Star: SM.onStar(); break;
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case AsmToken::LBrac: SM.onLBrac(); break;
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case AsmToken::RBrac: SM.onRBrac(); break;
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}
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if (!Done && UpdateLocLex) {
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End = Tok.getLoc();
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Parser.Lex(); // Consume the token.
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}
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}
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// Parse ][ as a plus.
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if (getLexer().is(AsmToken::RBrac)) {
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ExpectRBrac = false;
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End = Parser.getTok().getEndLoc();
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Parser.Lex();
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if (getLexer().is(AsmToken::LBrac)) {
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ExpectRBrac = true;
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Parser.Lex();
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if (getParser().ParseExpression(Disp, End))
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return 0;
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}
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} else if (ExpectRBrac) {
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if (getParser().ParseExpression(Disp, End))
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return 0;
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}
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if (ExpectRBrac) {
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if (getLexer().isNot(AsmToken::RBrac))
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return ErrorOperand(End, "expected ']' token!");
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End = Parser.getTok().getEndLoc();
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Parser.Lex();
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}
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if (!Disp)
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Disp = MCConstantExpr::Create(SM.getDisp(), getContext());
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// Parse the dot operator (e.g., [ebx].foo.bar).
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if (Tok.getString().startswith(".")) {
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@ -806,10 +989,18 @@ X86Operand *X86AsmParser::ParseIntelBracExpression(unsigned SegReg,
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Disp = NewDisp;
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}
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// handle [-42]
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if (!BaseReg && !IndexReg)
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return X86Operand::CreateMem(Disp, Start, End, Size);
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int BaseReg = SM.getBaseReg();
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int IndexReg = SM.getIndexReg();
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// handle [-42]
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if (!BaseReg && !IndexReg) {
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if (!SegReg)
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return X86Operand::CreateMem(Disp, Start, End);
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else
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return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, Start, End, Size);
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}
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int Scale = SM.getScale();
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return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
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Start, End, Size);
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}
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@ -56,13 +56,195 @@ _main:
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// CHECK: fld %st(0)
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fld ST(0)
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// CHECK: movl %fs:(%rdi), %eax
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mov EAX, DWORD PTR FS:[RDI]
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// CHECK: leal (,%rdi,4), %r8d
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lea R8D, DWORD PTR [4*RDI]
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// CHECK: movl _fnan(,%ecx,4), %ecx
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mov ECX, DWORD PTR [4*ECX + _fnan]
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// CHECK: movq %fs:320, %rax
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mov RAX, QWORD PTR FS:[320]
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// CHECK: vpgatherdd %xmm8, (%r15,%xmm9,2), %xmm1
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vpgatherdd XMM10, DWORD PTR [R15 + 2*XMM9], XMM8
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mov EAX, DWORD PTR FS:[RDI]
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// CHECK: leal (,%rdi,4), %r8d
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lea R8D, DWORD PTR [4*RDI]
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// CHECK: movl _fnan(,%ecx,4), %ecx
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mov ECX, DWORD PTR [4*ECX + _fnan]
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// CHECK: movq %fs:320, %rax
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mov RAX, QWORD PTR FS:[320]
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// CHECK: vpgatherdd %xmm8, (%r15,%xmm9,2), %xmm1
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vpgatherdd XMM10, DWORD PTR [R15 + 2*XMM9], XMM8
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// CHECK: movsd -8, %xmm5
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movsd XMM5, QWORD PTR [-8]
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// CHECK: movl %ecx, (%eax)
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mov [eax], ecx
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// CHECK: movl %ecx, (,%ebx,4)
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mov [4*ebx], ecx
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// CHECK: movl %ecx, (,%ebx,4)
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mov [ebx*4], ecx
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// CHECK: movl %ecx, 1024
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mov [1024], ecx
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// CHECK: movl %ecx, 4132
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mov [0x1024], ecx
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// CHECK: movl %ecx, 32
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mov [16 + 16], ecx
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// CHECK: movl %ecx, 0
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mov [16 - 16], ecx
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// CHECK: movl %ecx, 32
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mov [16][16], ecx
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// CHECK: movl %ecx, (%eax,%ebx,4)
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mov [eax + 4*ebx], ecx
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// CHECK: movl %ecx, (%eax,%ebx,4)
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mov [eax + ebx*4], ecx
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// CHECK: movl %ecx, (%eax,%ebx,4)
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mov [4*ebx + eax], ecx
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// CHECK: movl %ecx, (%eax,%ebx,4)
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mov [ebx*4 + eax], ecx
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// CHECK: movl %ecx, (%eax,%ebx,4)
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mov [eax][4*ebx], ecx
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// CHECK: movl %ecx, (%eax,%ebx,4)
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mov [eax][ebx*4], ecx
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// CHECK: movl %ecx, (%eax,%ebx,4)
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mov [4*ebx][eax], ecx
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// CHECK: movl %ecx, (%eax,%ebx,4)
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mov [ebx*4][eax], ecx
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// CHECK: movl %ecx, 12(%eax)
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mov [eax + 12], ecx
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// CHECK: movl %ecx, 12(%eax)
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mov [12 + eax], ecx
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// CHECK: movl %ecx, 32(%eax)
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mov [eax + 16 + 16], ecx
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// CHECK: movl %ecx, 32(%eax)
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mov [16 + eax + 16], ecx
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||||
// CHECK: movl %ecx, 32(%eax)
|
||||
mov [16 + 16 + eax], ecx
|
||||
// CHECK: movl %ecx, 12(%eax)
|
||||
mov [eax][12], ecx
|
||||
// CHECK: movl %ecx, 12(%eax)
|
||||
mov [12][eax], ecx
|
||||
// CHECK: movl %ecx, 32(%eax)
|
||||
mov [eax][16 + 16], ecx
|
||||
// CHECK: movl %ecx, 32(%eax)
|
||||
mov [eax + 16][16], ecx
|
||||
// CHECK: movl %ecx, 32(%eax)
|
||||
mov [eax][16][16], ecx
|
||||
// CHECK: movl %ecx, 32(%eax)
|
||||
mov [16][eax + 16], ecx
|
||||
// CHECK: movl %ecx, 32(%eax)
|
||||
mov [16 + eax][16], ecx
|
||||
// CHECK: movl %ecx, 32(%eax)
|
||||
mov [16][16 + eax], ecx
|
||||
// CHECK: movl %ecx, 32(%eax)
|
||||
mov [16 + 16][eax], ecx
|
||||
// CHECK: movl %ecx, 32(%eax)
|
||||
mov [eax][16][16], ecx
|
||||
// CHECK: movl %ecx, 32(%eax)
|
||||
mov [16][eax][16], ecx
|
||||
// CHECK: movl %ecx, 32(%eax)
|
||||
mov [16][16][eax], ecx
|
||||
// CHECK: movl %ecx, 16(,%ebx,4)
|
||||
mov [4*ebx + 16], ecx
|
||||
// CHECK: movl %ecx, 16(,%ebx,4)
|
||||
mov [ebx*4 + 16], ecx
|
||||
// CHECK: movl %ecx, 16(,%ebx,4)
|
||||
mov [4*ebx][16], ecx
|
||||
// CHECK: movl %ecx, 16(,%ebx,4)
|
||||
mov [ebx*4][16], ecx
|
||||
// CHECK: movl %ecx, 16(,%ebx,4)
|
||||
mov [16 + 4*ebx], ecx
|
||||
// CHECK: movl %ecx, 16(,%ebx,4)
|
||||
mov [16 + ebx*4], ecx
|
||||
// CHECK: movl %ecx, 16(,%ebx,4)
|
||||
mov [16][4*ebx], ecx
|
||||
// CHECK: movl %ecx, 16(,%ebx,4)
|
||||
mov [16][ebx*4], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [eax + 4*ebx + 16], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [eax + 16 + 4*ebx], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [4*ebx + eax + 16], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [4*ebx + 16 + eax], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [16 + eax + 4*ebx], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [16 + eax + 4*ebx], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [eax][4*ebx + 16], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [eax][16 + 4*ebx], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [4*ebx][eax + 16], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [4*ebx][16 + eax], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [16][eax + 4*ebx], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [16][eax + 4*ebx], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [eax + 4*ebx][16], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [eax + 16][4*ebx], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [4*ebx + eax][16], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [4*ebx + 16][eax], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [16 + eax][4*ebx], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [16 + eax][4*ebx], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [eax][4*ebx][16], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [eax][16][4*ebx], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [4*ebx][eax][16], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [4*ebx][16][eax], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [16][eax][4*ebx], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [16][eax][4*ebx], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [eax + ebx*4 + 16], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [eax + 16 + ebx*4], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [ebx*4 + eax + 16], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [ebx*4 + 16 + eax], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [16 + eax + ebx*4], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [16 + eax + ebx*4], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [eax][ebx*4 + 16], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [eax][16 + ebx*4], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [ebx*4][eax + 16], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [ebx*4][16 + eax], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [16][eax + ebx*4], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [16][eax + ebx*4], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [eax + ebx*4][16], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [eax + 16][ebx*4], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [ebx*4 + eax][16], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [ebx*4 + 16][eax], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [16 + eax][ebx*4], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [16 + eax][ebx*4], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [eax][ebx*4][16], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [eax][16][ebx*4], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [ebx*4][eax][16], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [ebx*4][16][eax], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [16][eax][ebx*4], ecx
|
||||
// CHECK: movl %ecx, 16(%eax,%ebx,4)
|
||||
mov [16][eax][ebx*4], ecx
|
||||
// CHECK: movl %ecx, -16(%eax,%ebx,4)
|
||||
mov [eax][ebx*4 - 16], ecx
|
||||
ret
|
||||
|
||||
Loading…
Reference in New Issue
Block a user